Hello Stefan, Am 26.03.2019 um 13:16 schrieb Stefan Roese:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected. If some boards need a different clock than the one provided with this patch, then support for this needs to be added later. Signed-off-by: Stefan Roese <s...@denx.de> Cc: Heiko Schocher <h...@denx.de> Cc: Andreas Bießmann <andr...@biessmann.org> Cc: Eugen Hristev <eugen.hris...@microchip.com> --- v2: - Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled drivers/serial/atmel_usart.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..049172baef 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };+#ifdef CONFIG_SPL_BUILD+static int atmel_serial_enable_clk(struct udevice *dev) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + /* Use fixed clock value in SPL */ + priv->usart_clk_rate = 132096000;
Hmm... could we have this value immediately configurable? Beside of this nitpick: Reviewed-by: Heiko Schocher <h...@denx.de> Tested on the taurus board: Tested-by: Heiko Schocher <h...@denx.de> bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
