Add the base SoC code for ST-Ericsson's Ux500 series of Cortex A9 based
SoCs.
Acked-by: Michael Brandt <michael.bra...@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vinc...@stericsson.com>
---
cpu/arm_cortexa9/ux500/Makefile | 45 ++++++++++++++++++
cpu/arm_cortexa9/ux500/clock.c | 56 +++++++++++++++++++++++
cpu/arm_cortexa9/ux500/cpu.c | 53 ++++++++++++++++++++++
include/asm-arm/arch-ux500/clock.h | 80 +++++++++++++++++++++++++++++++++
include/asm-arm/arch-ux500/hardware.h | 72 +++++++++++++++++++++++++++++
5 files changed, 306 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm_cortexa9/ux500/Makefile
create mode 100644 cpu/arm_cortexa9/ux500/clock.c
create mode 100644 cpu/arm_cortexa9/ux500/cpu.c
create mode 100644 include/asm-arm/arch-ux500/clock.h
create mode 100644 include/asm-arm/arch-ux500/hardware.h
diff --git a/cpu/arm_cortexa9/ux500/Makefile b/cpu/arm_cortexa9/ux500/Makefile
new file mode 100644
index 0000000..c671010
--- /dev/null
+++ b/cpu/arm_cortexa9/ux500/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS += clock.o cpu.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm_cortexa9/ux500/clock.c b/cpu/arm_cortexa9/ux500/clock.c
new file mode 100644
index 0000000..4d4ec13
--- /dev/null
+++ b/cpu/arm_cortexa9/ux500/clock.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2010 ST-Ericsson SA
+ * Author: Rabin Vincent <rabin.vinc...@stericsson.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clkrst {
+ unsigned int pcken;
+ unsigned int pckdis;
+ unsigned int kcken;
+ unsigned int kckdis;
+};
+
+static unsigned int clkrst_base[] = {
+ U8500_CLKRST1_BASE,
+ U8500_CLKRST2_BASE,
+ U8500_CLKRST3_BASE,
+ 0, /* No CLKRST for Periph4 */
+ U8500_CLKRST5_BASE,
+ U8500_CLKRST6_BASE,
+ U8500_CLKRST7_BASE,
+};
+
+/* Turn on peripheral clock at PRCC level */
+void u8500_clock_enable(int periph, int kern, int cluster)
+{
+ struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
+
+ if (kern != -1)
+ writel(1 << kern, &clkrst->kcken);
+
+ if (cluster != -1)
+ writel(1 << cluster, &clkrst->pcken);
+}
diff --git a/cpu/arm_cortexa9/ux500/cpu.c b/cpu/arm_cortexa9/ux500/cpu.c
new file mode 100644
index 0000000..98f0802
--- /dev/null
+++ b/cpu/arm_cortexa9/ux500/cpu.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2010 ST-Ericsson SA
+ * Author: Rabin Vincent <rabin.vinc...@stericsson.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <nomadik.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NOMADIK_GPIO
+unsigned long nmk_gpio_base[CONFIG_NOMADIK_GPIO_NUM_BANKS] = {
+ U8500_GPIO0_BASE,
+ U8500_GPIO1_BASE,
+ U8500_GPIO2_BASE,
+ U8500_GPIO3_BASE,
+ U8500_GPIO4_BASE,
+ U8500_GPIO5_BASE,
+ U8500_GPIO6_BASE,
+ U8500_GPIO7_BASE,
+ U8500_GPIO8_BASE
+};
+#endif
+
+void reset_cpu(unsigned long ignored)
+{
+ struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
+
+ writel(0x1, &prcmu->ape_softrst);
+
+ while (1)
+ ; /* infinite loop until reset */
+}
diff --git a/include/asm-arm/arch-ux500/clock.h
b/include/asm-arm/arch-ux500/clock.h
new file mode 100644
index 0000000..b674699
--- /dev/null
+++ b/include/asm-arm/arch-ux500/clock.h
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2010 ST-Ericsson SA
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK
+#define __ASM_ARCH_CLOCK
+
+#define PRCM_TCR_DOZE_MODE (1 << 17)
+#define PRCM_CLKMGT_ENABLE (1 << 8)
+
+/* Arguments to u8500_clock_enable() */
+#define U8500_CLK(periph, kern, cluster) periph, kern, cluster
+#define U8500_CLK_MTU0 U8500_CLK(7, 2, -1)
+#define U8500_CLK_UART2 U8500_CLK(3, 6, 6)
+
+struct prcmu {
+ unsigned int armclkfix_mgt;
+ unsigned int armclk_mgt;
+ unsigned int svammdspclk_mgt;
+ unsigned int siammdspclk_mgt;
+ unsigned int reserved;
+ unsigned int sgaclk_mgt;
+ unsigned int uartclk_mgt;
+ unsigned int msp02clk_mgt;
+ unsigned int i2cclk_mgt;
+ unsigned int sdmmcclk_mgt;
+ unsigned int slimclk_mgt;
+ unsigned int per1clk_mgt;
+ unsigned int per2clk_mgt;
+ unsigned int per3clk_mgt;
+ unsigned int per5clk_mgt;
+ unsigned int per6clk_mgt;
+ unsigned int per7clk_mgt;
+ unsigned int lcdclk_mgt;
+ unsigned int reserved1;
+ unsigned int bmlclk_mgt;
+ unsigned int hsitxclk_mgt;
+ unsigned int hsirxclk_mgt;
+ unsigned int hdmiclk_mgt;
+ unsigned int apeatclk_mgt;
+ unsigned int apetraceclk_mgt;
+ unsigned int mcdeclk_mgt;
+ unsigned int ipi2cclk_mgt;
+ unsigned int dsialtclk_mgt;
+ unsigned int spare2clk_mgt;
+ unsigned int dmaclk_mgt;
+ unsigned int b2r2clk_mgt;
+ unsigned int tvclk_mgt;
+ unsigned int unused[82];
+ unsigned int tcr;
+ unsigned int unused1[23];
+ unsigned int ape_softrst;
+};
+
+extern void u8500_clock_enable(int periph, int kern, int cluster);
+
+static inline void u8500_prcmu_enable(unsigned int *reg)
+{
+ writel(readl(reg) | PRCM_CLKMGT_ENABLE, reg);
+}
+
+#endif /* __ASM_ARCH_CLOCK */
diff --git a/include/asm-arm/arch-ux500/hardware.h
b/include/asm-arm/arch-ux500/hardware.h
new file mode 100644
index 0000000..5f32eaa
--- /dev/null
+++ b/include/asm-arm/arch-ux500/hardware.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2010 ST-Ericsson SA
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Peripheral clusters */
+#define U8500_PER3_BASE 0x80000000
+#define U8500_PER2_BASE 0x80110000
+#define U8500_PER1_BASE 0x80120000
+#define U8500_PER4_BASE 0x80150000
+#define U8500_PER6_BASE 0xa03c0000
+#define U8500_PER7_BASE 0xa03d0000
+#define U8500_PER5_BASE 0xa03e0000
+
+/* GPIO */
+#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
+#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80)
+#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000)
+#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80)
+#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100)
+#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180)
+#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000)
+#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80)
+#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000)
+
+/* Per7 */
+#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
+#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
+#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
+
+/* Per6 */
+#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
+
+/* Per5 */
+#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
+
+/* Per4 */
+#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
+
+/* Per3 */
+#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
+#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
+
+/* Per2 */
+#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
+
+/* Per1 */
+#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
+#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
--
1.7.0
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