Eliminate register address #defines by using C structs, and move the
rest of the header contents into timer.c.
Cc: Alessandro Rubini <rub...@unipv.it>
Acked-by: Michael Brandt <michael.bra...@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vinc...@stericsson.com>
---
cpu/arm926ejs/nomadik/timer.c | 45 ++++++++++++++++++------
include/asm-arm/arch-nomadik/mtu.h | 66 ------------------------------------
2 files changed, 34 insertions(+), 77 deletions(-)
delete mode 100644 include/asm-arm/arch-nomadik/mtu.h
diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c
index fdab650..0aeeb63 100644
--- a/cpu/arm926ejs/nomadik/timer.c
+++ b/cpu/arm926ejs/nomadik/timer.c
@@ -22,7 +22,25 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/mtu.h>
+
+struct mtu {
+ uint imsc;
+ uint ris;
+ uint mis;
+ uint icr;
+ struct mtu_timer {
+ uint lr;
+ uint val;
+ uint cr;
+ uint bglr;
+ } timer[4];
+};
+
+#define MTU_CRn_ENA 0x80
+#define MTU_CRn_PRESCALE_1 0x00
+#define MTU_CRn_PRESCALE_16 0x04
+#define MTU_CRn_PRESCALE_256 0x08
+#define MTU_CRn_32BITS 0x02
/*
* The timer is a decrementer, we'll left it free running at 2.4MHz.
@@ -32,14 +50,19 @@
#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
-/* macro to read the decrementing 32 bit timer as an increasing count */
-#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
+static const struct mtu_timer *timer
+ = &((struct mtu *) CONFIG_SYS_TIMERBASE)->timer[0];
+
+/* read the decrementing 32 bit timer as an increasing count */
+static ulong read_timer(void)
+{
+ return 0 - readl(&timer->val);
+}
/* Configure a free-running, auto-wrap counter with no prescaler */
int timer_init(void)
{
- writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
- CONFIG_SYS_TIMERBASE + MTU_CR(0));
+ writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, &timer->cr);
reset_timer();
return 0;
}
@@ -48,21 +71,21 @@ int timer_init(void)
void reset_timer(void)
{
ulong val;
- writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
+ writel(0, &timer->lr);
/*
* The load-register isn't really immediate: it changes on clock
* edges, so we must wait for our newly-written value to appear.
* Since we might miss reading 0, wait for any change in value.
*/
- val = READ_TIMER();
- while (READ_TIMER() == val)
+ val = read_timer();
+ while (read_timer() == val)
;
}
/* Return how many HZ passed since "base" */
ulong get_timer(ulong base)
{
- ulong hz = READ_TIMER() / (TIMER_CLOCK / CONFIG_SYS_HZ);
+ ulong hz = read_timer() / (TIMER_CLOCK / CONFIG_SYS_HZ);
return hz - base;
}
@@ -71,8 +94,8 @@ void __udelay(unsigned long usec)
{
ulong ini, end;
- ini = READ_TIMER();
+ ini = read_timer();
end = ini + USEC_TO_COUNT(usec);
- while ((signed)(end - READ_TIMER()) > 0)
+ while ((signed)(end - read_timer()) > 0)
;
}
diff --git a/include/asm-arm/arch-nomadik/mtu.h
b/include/asm-arm/arch-nomadik/mtu.h
deleted file mode 100644
index a87be9e..0000000
--- a/include/asm-arm/arch-nomadik/mtu.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MTU_H
-#define __ASM_ARCH_MTU_H
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
-#define MTU_RIS 0x04 /* Raw interrupt status */
-#define MTU_MIS 0x08 /* Masked interrupt status */
-#define MTU_ICR 0x0C /* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
-#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
-#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
-#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
-
-/* bits for the control register */
-#define MTU_CRn_ENA 0x80
-#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK 0x0c
-#define MTU_CRn_PRESCALE_1 0x00
-#define MTU_CRn_PRESCALE_16 0x04
-#define MTU_CRn_PRESCALE_256 0x08
-#define MTU_CRn_32BITS 0x02
-#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from
BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR 0xff0
-#define MTU_ITOP 0xff4
-
-#define MTU_PERIPH_ID0 0xfe0
-#define MTU_PERIPH_ID1 0xfe4
-#define MTU_PERIPH_ID2 0xfe8
-#define MTU_PERIPH_ID3 0xfeC
-
-#define MTU_PCELL0 0xff0
-#define MTU_PCELL1 0xff4
-#define MTU_PCELL2 0xff8
-#define MTU_PCELL3 0xffC
-
-#endif /* __ASM_ARCH_MTU_H */
--
1.7.0
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