Hi, On Tuesday 03 October 2017 06:48 PM, Marek Vasut wrote: > On 10/03/2017 03:17 PM, Faiz Abbas wrote: >> Hi, >> >> On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote: >>> On 09/19/2017 01:15 PM, Faiz Abbas wrote: >>>> A flush of the cache is required before any DMA access can take place. >>> >>> You mean invalidation for inbound DMA, flush for outbound DMA, right ? >> >> yes thats what i meant. >> >> >>>> >>>> - dwc3_flush_cache((uintptr_t)trb, sizeof(*trb)); >>>> + dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) * 2); >>> >>> Why *2 ? >> >> Because its allocated as sizeof(*dwc->ep0_trb) * 2 below. This is not >> strictly required as dwc3_flush_cache() rounds up the size to >> CACHELINE_SIZE but from a caller POV, flush everything we allocated. > > Can the other TRB be in use ? Maybe aligning the TRBs to cacheline size > would be better ? > A single trb is 16 bytes in size and two of them are allocated contiguously. Originally, a flush on the first trb was flushing both of them anyway as the minimum flush is CACHELINE_SIZE (64 bytes). This is not changing any functionality as far as I have tested. Just making sure cache misaligned warnings don't show up.
Thanks, Faiz _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
