Hi, On Tuesday 19 September 2017 04:45 PM, Faiz Abbas wrote: > A flush of the cache is required before any DMA access can take place. > The minimum size that can be flushed from the cache is one cache line > size. Therefore, any buffer allocated for DMA should be in multiples > of cache line size. > > Thus, allocate memory for ep0_trb in multiples of cache line size. > > Also, when local variable trb is assigned to dwc->ep0_trb[1] and used > to flush cache, it leads to cache misaligned messages as only the base > address dwc->ep0_trb is cache aligned. > > Therefore, flush cache using ep0_trb_addr which is always cache aligned. > > Signed-off-by: Faiz Abbas <faiz_ab...@ti.com>
Gentle ping. Thanks, Faiz _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
