On 10/04/2017 03:11 PM, Faiz Abbas wrote: > Hi, > > On Wednesday 04 October 2017 06:01 PM, Marek Vasut wrote: >> On 10/04/2017 12:51 PM, Faiz Abbas wrote: >>> Hi, >>> On Tuesday 03 October 2017 06:48 PM, Marek Vasut wrote: >>>> On 10/03/2017 03:17 PM, Faiz Abbas wrote: >>>>> Hi, >>>>> On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote: >>>>>> On 09/19/2017 01:15 PM, Faiz Abbas wrote: >>>>>>> >>>>>>> - dwc3_flush_cache((uintptr_t)trb, sizeof(*trb)); >>>>>>> + dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) * >>>>>>> 2); >>>>>> >>>>>> Why *2 ? >>>>> >>>>> Because its allocated as sizeof(*dwc->ep0_trb) * 2 below. This is not >>>>> strictly required as dwc3_flush_cache() rounds up the size to >>>>> CACHELINE_SIZE but from a caller POV, flush everything we allocated. >>>> >>>> Can the other TRB be in use ? Maybe aligning the TRBs to cacheline size >>>> would be better ? >>>> >>> A single trb is 16 bytes in size and two of them are allocated >>> contiguously. >> >> Why are two allocated continuously ? (I am not dwc3 expert) > > Neither am I. I did try to pad to the dwc_trb structure such that each > trb is 64 bytes in size but this leads to failures when testing. I > didn't get a chance to debug this though. I suspect its because the code > expects the trbs to be contiguous and/or 16 bytes in size.
Maybe that's something you need to check -- why it fails if aligned . Do the TRBs need to be stored back-to-back ? > It'll be great if someone can shed light on this. > >> >>> Originally, a flush on the first trb was flushing both of >>> them anyway as the minimum flush is CACHELINE_SIZE (64 bytes). This is >>> not changing any functionality as far as I have tested. Just making sure >>> cache misaligned warnings don't show up. >> >> If you flush 64bytes, you flush more than 2 TRBs, you flush something >> around those TRBs too. > > Yes and that is why I changed the allocation step to > ROUND(sizeof(trb) * 2, 64). We use only 32 bytes for two trbs but make > sure to allocate 64 bytes so that we can safely flush it. > > Thanks > Faiz > -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
