Dear Paul Gortmaker, In message <8c4c3a2e238ee8ef67637f499cc3269acbb1bf00.1253315004.git.paul.gortma...@windriver.com> you wrote: > The size of the LB SDRAM on this board is 128MB, spanning CS3 > and CS4. It was previously only being configured for 64MB on > CS3, since that was what the original codebase of the MPC8548CDS > had. In addition to setting up BR4/OR4, this also adds the TLB > entry for the second half of the SDRAM. ... > + * TLB 6: 64M Cacheable, non-guarded > + * 0xf4000000 64M LBC SDRAM Second half > + */ > + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, > CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
Line too long. Please check globally. ... > SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH > + 0x400000, Please also fix this one, while you are there. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Of all the things I've lost, I miss my mind the most. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
