On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
> The size of the LB SDRAM on this board is 128MB, spanning CS3
> and CS4. It was previously only being configured for 64MB on
> CS3, since that was what the original codebase of the MPC8548CDS
> had. In addition to setting up BR4/OR4, this also adds the TLB
> entry for the second half of the SDRAM.
>
> Signed-off-by: Paul Gortmaker <paul.gortma...@windriver.com>
> ---
> board/sbc8548/sbc8548.c | 8 +++++++-
> board/sbc8548/tlb.c | 22 +++++++++++++++-------
> include/configs/sbc8548.h | 42 ++++++++++++++++++++++++++++++++++++
> ++----
> 3 files changed, 60 insertions(+), 12 deletions(-)
>
> diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
> index 3104d37..1db32ec 100644
> --- a/board/sbc8548/sbc8548.c
> +++ b/board/sbc8548/sbc8548.c
> @@ -152,7 +152,7 @@ local_bus_init(void)
> void
> sdram_init(void)
> {
> -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
> +#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
>
> uint idx;
> volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
> @@ -172,6 +172,12 @@ sdram_init(void)
> lbc->br3 = CONFIG_SYS_BR3_PRELIM;
> asm("msync");
>
> + lbc->or4 = CONFIG_SYS_OR4_PRELIM;
> + asm("msync");
> +
> + lbc->br4 = CONFIG_SYS_BR4_PRELIM;
> + asm("msync");
> +
> lbc->lbcr = CONFIG_SYS_LBC_LBCR;
> asm("msync");
it would be nice to move this to using IO accessors (out_be32)
- k
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