> -----Original Message----- > From: Simon Kagstrom [mailto:simon.kagst...@netinsight.net] > Sent: Friday, September 11, 2009 1:45 PM > To: U-Boot ML > Cc: Prafulla Wadaskar; Dhaval Vasa; Prabhanjan Sarnaik; Ashish Karkare > Subject: [PATCH v2] Support for the OpenRD base board > > Support for the OpenRD base board > > The implementation is borrowed from the sheevaplug board and > the Marvell > 1.1.4 code and likely to be a bit incomplete. > > Signed-off-by: Simon Kagstrom <simon.kagst...@netinsight.net> > --- > The configuration does not include UBIFS support, which still needs > he remaining patches for the bitops cleanup and fixes: Pls correct typo here
> > http://lists.denx.de/pipermail/u-boot/2009-August/059285.html > > to build. Until those are applied, it's turned off here. > > > I get run-time problems when building for armv5te for OpenRD base > (apparently the same problem occurs for other Kirkwood boards). This > patch fixes that: > > http://lists.denx.de/pipermail/u-boot/2009-September/059896.html > > > The second version contains the kwbimage.cfg needed to > produce an image > to install on the NAND flash. > > MAINTAINERS | 4 + > MAKEALL | 1 + > Makefile | 3 + > board/Marvell/openrd_base/Makefile | 51 +++++++ > board/Marvell/openrd_base/config.mk | 28 ++++ > board/Marvell/openrd_base/kwbimage.cfg | 168 > ++++++++++++++++++++++++ > board/Marvell/openrd_base/openrd_base.c | 158 ++++++++++++++++++++++ > board/Marvell/openrd_base/openrd_base.h | 46 +++++++ > include/configs/openrd_base.h | 218 > +++++++++++++++++++++++++++++++ > 9 files changed, 677 insertions(+), 0 deletions(-) > create mode 100644 board/Marvell/openrd_base/Makefile > create mode 100644 board/Marvell/openrd_base/config.mk > create mode 100644 board/Marvell/openrd_base/kwbimage.cfg > create mode 100644 board/Marvell/openrd_base/openrd_base.c > create mode 100644 board/Marvell/openrd_base/openrd_base.h > create mode 100644 include/configs/openrd_base.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index e9db278..99cdc12 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -588,6 +588,10 @@ Gary Jennejohn <ga...@denx.de> > Konstantin Kletschke <kletsc...@synertronixx.de> > scb9328 ARM920T > > +Simon Kagstrom <simon.kagst...@netinsight.net> > + > + openrd_base ARM926EJS (Kirkwood SoC) > + > Nishant Kamat <nska...@ti.com> > > omap1610h2 ARM926EJS > diff --git a/MAKEALL b/MAKEALL > index f0ed8ea..9e6eee2 100755 > --- a/MAKEALL > +++ b/MAKEALL > @@ -533,6 +533,7 @@ LIST_ARM9=" \ > omap1610inn \ > omap5912osk \ > omap730p2 \ > + openrd_base \ > rd6281a \ > sbc2410x \ > scb9328 \ > diff --git a/Makefile b/Makefile > index 9764cea..6cef82a 100644 > --- a/Makefile > +++ b/Makefile > @@ -3022,6 +3022,9 @@ omap1610h2_cs_autoboot_config: unconfig > omap5912osk_config : unconfig > @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk ti omap > > +openrd_base_config: unconfig > + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) > Marvell kirkwood > + > xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, > $(subst _config,,$1))) > > omap730p2_config \ > diff --git a/board/Marvell/openrd_base/Makefile > b/board/Marvell/openrd_base/Makefile > new file mode 100644 > index 0000000..defbb08 > --- /dev/null > +++ b/board/Marvell/openrd_base/Makefile > @@ -0,0 +1,51 @@ > +# > +# (C) Copyright 2009 > +# Marvell Semiconductor <www.marvell.com> > +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> I think you must add your reference here.. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > +# MA 02110-1301 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).a > + > +COBJS := openrd_base.o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) > + > +clean: > + rm -f $(SOBJS) $(OBJS) > + > +distclean: clean > + rm -f $(LIB) core *.bak .depend > + > +############################################################# > ############ > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +############################################################# > ############ > diff --git a/board/Marvell/openrd_base/config.mk > b/board/Marvell/openrd_base/config.mk > new file mode 100644 > index 0000000..2bd9f79 > --- /dev/null > +++ b/board/Marvell/openrd_base/config.mk > @@ -0,0 +1,28 @@ > +# > +# (C) Copyright 2009 > +# Marvell Semiconductor <www.marvell.com> > +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> Same here > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > +# MA 02110-1301 USA > +# > + > +TEXT_BASE = 0x00600000 > + > +# Kirkwood Boot Image configuration file > +KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg > diff --git a/board/Marvell/openrd_base/kwbimage.cfg > b/board/Marvell/openrd_base/kwbimage.cfg > new file mode 100644 > index 0000000..1228ac8 > --- /dev/null > +++ b/board/Marvell/openrd_base/kwbimage.cfg > @@ -0,0 +1,168 @@ > +# > +# (C) Copyright 2009 > +# Marvell Semiconductor <www.marvell.com> > +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > +# MA 02110-1301 USA > +# > +# Refer docs/README.kwimage for more details about how-to configure > +# and create kirkwood boot image > +# > + > +# Boot Media configurations > +BOOT_FROM nand > +NAND_ECC_MODE default > +NAND_PAGE_SIZE 0x0800 > + > +# SOC registers configuration using bootrom header extension > +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed > + > +# Configure RGMII-0 interface pad voltage to 1.8V > +DATA 0xFFD100e0 0x1b1b1b9b > + > +#Dram initalization for SINGLE x16 CL=5 @ 400MHz > +DATA 0xFFD01400 0x43000c30 # DDR Configuration register > +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) > +# bit23-14: zero > +# bit24: 1= enable exit self refresh mode on DDR access > +# bit25: 1 required > +# bit29-26: zero > +# bit31-30: 01 > + > +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low > +# bit 4: 0=addr/cmd in smame cycle > +# bit 5: 0=clk is driven during self refresh, we don't > care for APX > +# bit 6: 0=use recommended falling edge of clk for addr/cmd > +# bit14: 0=input buffer always powered up > +# bit18: 1=cpu lock transaction enabled > +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL > disabled bit31=0 > +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs > 400MHz, unbuffered DIMM > +# bit30-28: 3 required > +# bit31: 0=no additional STARTBURST delay > + > +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active > cycles value +1) > +# bit3-0: TRAS lsbs > +# bit7-4: TRCD > +# bit11- 8: TRP > +# bit15-12: TWR > +# bit19-16: TWTR > +# bit20: TRAS msb > +# bit23-21: 0x0 > +# bit27-24: TRRD > +# bit31-28: TRTP > + > +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) > +# bit6-0: TRFC > +# bit8-7: TR2R > +# bit10-9: TR2W > +# bit12-11: TW2W > +# bit31-13: zero required > + > +DATA 0xFFD01410 0x000000cc # DDR Address Control > +# bit1-0: 00, Reserved This means 0x8 not reserved as per rev-C specification document > +# bit3-2: 11, Cs0size=1Gb > +# bit5-4: 00, Reserved Ditto > +# bit7-6: 11, Cs1size=1Gb > +# bit9-8: 00, Cs2width=nonexistent > +# bit11-10: 00, Cs2size =nonexistent > +# bit13-12: 00, Cs3width=nonexistent > +# bit15-14: 00, Cs3size =nonexistent > +# bit16: 0, Cs0AddrSel > +# bit17: 0, Cs1AddrSel > +# bit18: 0, Cs2AddrSel > +# bit19: 0, Cs3AddrSel > +# bit31-20: 0 required > + > +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control > +# bit0: 0, OpenPage enabled > +# bit31-1: 0 required > + > +DATA 0xFFD01418 0x00000000 # DDR Operation > +# bit3-0: 0x0, DDR cmd > +# bit31-4: 0 required > + > +DATA 0xFFD0141C 0x00000C52 # DDR Mode > +# bit2-0: 2, BurstLen=2 required > +# bit3: 0, BurstType=0 required > +# bit6-4: 4, CL=5 > +# bit7: 0, TestMode=0 normal > +# bit8: 0, DLL reset=0 normal > +# bit11-9: 6, auto-precharge write recovery ???????????? > +# bit12: 0, PD must be zero > +# bit31-13: 0 required > + > +DATA 0xFFD01420 0x00000042 # DDR Extended Mode > +# bit0: 0, DDR DLL enabled > +# bit1: 1, DDR drive strength reduced > +# bit2: 0, DDR ODT control lsd (disabled) > +# bit5-3: 000, required > +# bit6: 1, DDR ODT control msb, (disabled) > +# bit9-7: 000, required > +# bit10: 0, differential DQS enabled > +# bit11: 0, required > +# bit12: 0, DDR output buffer enabled > +# bit31-13: 0 required > + > +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High > +# bit2-0: 111, required > +# bit3 : 1 , MBUS Burst Chop disabled > +# bit6-4: 111, required > +# bit7 : 0 > +# bit8 : 1 , add writepath sample stage, must be 1 for > DDR freq >= 300MHz > +# bit9 : 0 , no half clock cycle addition to dataout > +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals > +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh > +# bit15-12: 1111 required > +# bit31-16: 0 required > + > +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) > +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) > + > +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 > +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size > +# bit0: 1, Window enabled > +# bit1: 0, Write Protect disabled > +# bit3-2: 00, CS0 hit selected > +# bit23-4: ones, required > +# bit31-24: 0x0F, Size (i.e. 256MB) > + > +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb > +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window > enabled for CS1 > + > +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled > +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled > + > +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) > +# bit3-0: 0010, (read) M_ODT[0] is asserted during read > from DRAM CS1 > +# bit7-4: 0001, (read) M_ODT[1] is asserted during read > from DRAM CS0 > +# bit19-16: 0010, (write) M_ODT[0] is asserted during write > to DRAM CS1. > +# bit23-20: 0001, (write) M_ODT[1] is asserted during write > to DRAM CS0. > +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) > + > +DATA 0xFFD0149C 0x0000E40f # CPU ODT Control > +# bit3-0: 1111, internal ODT is asserted during read from > DRAM bank 0-3 > +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT > Select: 150 ohm > +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm > +# bit14: 1, M_STARTBURST_IN ODT: Enabled > +# bit15: 1, DDR IO ODT Unit: Use ODT block > +DATA 0xFFD01480 0x00000001 # DDR Initialization Control > +#bit0=1, enable DDR init upon this register write > + > +# End of Header extension > +DATA 0x0 0x0 > diff --git a/board/Marvell/openrd_base/openrd_base.c > b/board/Marvell/openrd_base/openrd_base.c > new file mode 100644 > index 0000000..4c9a848 > --- /dev/null > +++ b/board/Marvell/openrd_base/openrd_base.c > @@ -0,0 +1,158 @@ > +/* > + * (C) Copyright 2009 > + * Net Insight <www.netinsight.net> > + * Written-by: Simon Kagstrom <simon.kagst...@netinsight.net> > + * > + * Based on sheevaplug.c: > + * (C) Copyright 2009 > + * Marvell Semiconductor <www.marvell.com> > + * Written-by: Prafulla Wadaskar <prafu...@marvell.com> You can follow the same documentation for above files > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > + * MA 02110-1301 USA > + */ > + > +#include <common.h> > +#include <miiphy.h> > +#include <asm/arch/kirkwood.h> > +#include <asm/arch/mpp.h> > +#include "openrd_base.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int board_init(void) > +{ > + /* > + * default gpio configuration > + * There are maximum 64 gpios controlled through 2 sets > of registers > + * the below configuration configures mainly initial LED status > + */ > + kw_config_gpio(OPENRD_OE_VAL_LOW, > + OPENRD_OE_VAL_HIGH, > + OPENRD_OE_LOW, OPENRD_OE_HIGH); > + > + /* Multi-Purpose Pins Functionality configuration */ > + u32 kwmpp_config[] = { > + MPP0_NF_IO2, > + MPP1_NF_IO3, > + MPP2_NF_IO4, > + MPP3_NF_IO5, > + MPP4_NF_IO6, > + MPP5_NF_IO7, > + MPP6_SYSRST_OUTn, > + MPP7_GPO, > + MPP8_TW_SDA, > + MPP9_TW_SCK, > + MPP10_UART0_TXD, > + MPP11_UART0_RXD, > + MPP12_SD_CLK, > + MPP13_SD_CMD, /* Alt UART1_TXD */ > + MPP14_SD_D0, /* Alt UART1_RXD */ > + MPP15_SD_D1, > + MPP16_SD_D2, > + MPP17_SD_D3, > + MPP18_NF_IO0, > + MPP19_NF_IO1, > + MPP20_GE1_0, > + MPP21_GE1_1, > + MPP22_GE1_2, > + MPP23_GE1_3, > + MPP24_GE1_4, > + MPP25_GE1_5, > + MPP26_GE1_6, > + MPP27_GE1_7, > + MPP28_GPIO, > + MPP29_TSMP9, > + MPP30_GE1_10, > + MPP31_GE1_11, > + MPP32_GE1_12, > + MPP33_GE1_13, > + MPP34_GPIO, /* UART1 / SD sel */ > + MPP35_TDM_CH0_TX_QL, > + MPP36_TDM_SPI_CS1, > + MPP37_TDM_CH2_TX_QL, > + MPP38_TDM_CH2_RX_QL, > + MPP39_AUDIO_I2SBCLK, > + MPP40_AUDIO_I2SDO, > + MPP41_AUDIO_I2SLRC, > + MPP42_AUDIO_I2SMCLK, > + MPP43_AUDIO_I2SDI, > + MPP44_AUDIO_EXTCLK, > + MPP45_TDM_PCLK, > + MPP46_TDM_FS, > + MPP47_TDM_DRX, > + MPP48_TDM_DTX, > + MPP49_TDM_CH0_RX_QL, > + 0 > + }; Looks better if empty line can be inserted here > + kirkwood_mpp_conf(kwmpp_config); > + > + /* > + * arch number of board > + */ > + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; > + > + /* adress of boot parameters */ > + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; > + return 0; Pls correct indentation b y using tabs only here and everywhere > +} > + > +int dram_init(void) > +{ > + int i; > + > + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { > + gd->bd->bi_dram[i].start = kw_sdram_bar(i); > + gd->bd->bi_dram[i].size = kw_sdram_bs(i); > + } > + return 0; > +} > + > +#ifdef CONFIG_RESET_PHY_R > +void reset_phy(void) > +{ > + u16 reg; > + u16 devadr; > + char *name = "egiga0"; > + > + if (miiphy_set_current_dev(name)) > + return; > + > + /* command to read PHY dev address */ > + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { > + printf("Err..%s could not read PHY dev address\n", > + __FUNCTION__); > + return; > + } > + > + /* > + * Enable RGMII delay on Tx and Rx for CPU port > + * Ref: sec 4.7.2 of chip datasheet > + */ > + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); > + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); > + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); > + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); > + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); > + > + /* reset the phy */ > + miiphy_reset(name, devadr); > + > + printf("88E1116 Initialized on %s\n", name); > +} > +#endif /* CONFIG_RESET_PHY_R */ > diff --git a/board/Marvell/openrd_base/openrd_base.h > b/board/Marvell/openrd_base/openrd_base.h > new file mode 100644 > index 0000000..f3daf17 > --- /dev/null > +++ b/board/Marvell/openrd_base/openrd_base.h > @@ -0,0 +1,46 @@ > +/* > + * (C) Copyright 2009 > + * Net Insight <www.netinsight.net> > + * Written-by: Simon Kagstrom <simon.kagst...@netinsight.net> > + * > + * Based on sheevaplug.h: > + * (C) Copyright 2009 > + * Marvell Semiconductor <www.marvell.com> > + * Written-by: Prafulla Wadaskar <prafu...@marvell.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > + * MA 02110-1301 USA > + */ > + > +#ifndef __OPENRD_BASE_H > +#define __OPENRD_BASE_H > + > +#define OPENRD_OE_LOW (~(1<<28)) /* > RS232 / RS485 */ > +#define OPENRD_OE_HIGH (~(1<<2)) /* SD > / UART1 */ > +#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ > +#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ > + > +/* PHY related */ > +#define MV88E1116_LED_FCTRL_REG 10 > +#define MV88E1116_CPRSP_CR3_REG 21 > +#define MV88E1116_MAC_CTRL_REG 21 > +#define MV88E1116_PGADR_REG 22 > +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) > +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) > + > +#endif /* __OPENRD_BASE_H */ > diff --git a/include/configs/openrd_base.h > b/include/configs/openrd_base.h > new file mode 100644 > index 0000000..ebda0c5 > --- /dev/null > +++ b/include/configs/openrd_base.h > @@ -0,0 +1,218 @@ > +/* > + * (C) Copyright 2009 > + * Net Insight <www.netinsight.net> > + * Written-by: Simon Kagstrom <simon.kagst...@netinsight.net> > + * > + * Based on sheevaplug.h: > + * (C) Copyright 2009 > + * Marvell Semiconductor <www.marvell.com> > + * Written-by: Prafulla Wadaskar <prafu...@marvell.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > + * MA 02110-1301 USA > + */ > + > +#ifndef _CONFIG_OPENRD_BASE_H > +#define _CONFIG_OPENRD_BASE_H > + > +/* > + * Version number information > + */ > +#define CONFIG_IDENT_STRING "\nMarvell-OpenRD_base" Is this name in synce with what you have registered on armlinux with machin-id? Can you pls use short name here? > + > +/* > + * High Level Configuration Options (easy to change) > + */ > +#define CONFIG_MARVELL 1 > +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ > +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core > subversion */ Pls Use CONFIG_SHEEVA_88SV131 here > +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ > +#define CONFIG_KW88F6281 1 /* SOC Name */ > +#define CONFIG_MACH_OPENRD_BASE /* Machine type */ > + > +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 > support */ > +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board > lowlevel_init */ > +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 > for kernel */ > +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII > Pad voltage to 1.8V */ Does this board have PCI interface, if yet then pls include following line #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ > +#define CONFIG_MV88E1116 /* Support for the > MV88E1116 PHY */ > + > +/* > + * CLKs configurations > + */ > +#define CONFIG_SYS_HZ 1000 > + > +/* > + * NS16550 Configuration > + */ > +#define CONFIG_SYS_NS16550 > +#define CONFIG_SYS_NS16550_SERIAL > +#define CONFIG_SYS_NS16550_REG_SIZE (-4) > +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK > +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE > + > +/* > + * Serial Port configuration > + * The following definitions let you select what serial you > want to use > + * for your console driver. > + */ > + > +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ > +#define CONFIG_BAUDRATE 115200 > +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ > + 115200,230400, > 460800, 921600 } > +/* auto boot */ > +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ > + > +/* > + * For booting Linux, the board info and command line data > + * have to be in the first 8 MB of memory, since this is > + * the maximum mapped by the Linux kernel during initialization. > + */ > +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ > +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ > +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ > + > +#define CONFIG_SYS_PROMPT "Marvell>> " /* > Command Prompt */ > +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O > Buff Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ > + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ > +/* > + * Commands configuration > + */ > +#define CONFIG_CMD_AUTOSCRIPT > +#define CONFIG_CMD_BOOTD > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_ENV > +#define CONFIG_CMD_FAT > +#define CONFIG_CMD_LOADB > +#define CONFIG_CMD_MEMORY > +#define CONFIG_CMD_NAND > +#define CONFIG_CMD_NET > +#define CONFIG_CMD_MII > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_RUN > +#define CONFIG_CMD_SAVEENV > +#define CONFIG_CMD_USB > +#define CONFIG_CMD_IMI Again I suggest to use config_cmd_default.h here :-) to bring it in sync with other Marvell and arm boards configuration > +/* > + * Flash configuration > + */ > +#ifndef CONFIG_CMD_FLASH > +#define CONFIG_SYS_NO_FLASH 1 /* Declare no > flash (NOR/SPI) */ > +#endif > + > +/* > + * NAND configuration > + */ > +#ifdef CONFIG_CMD_NAND > +#define CONFIG_NAND_KIRKWOOD > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > +#define NAND_MAX_CHIPS 1 > +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* > KW_DEFADR_NANDF */ > +#define NAND_ALLOW_ERASE_ALL 1 > +#endif > + > +/* > + * Environment variables configurations > + */ > +#ifdef CONFIG_CMD_NAND > +#define CONFIG_ENV_IS_IN_NAND 1 > +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ > +#else > +#define CONFIG_ENV_IS_NOWHERE 1 /* if > env in SDRAM */ > +#endif > +/* > + * max 4k env size is enough, but in case of nand > + * it has to be rounded to sector size > + */ > +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ > +#define CONFIG_ENV_ADDR 0xa0000 > +#define CONFIG_ENV_OFFSET 0xa0000 /* env starts here */ Do you really need this address? the u-boot binary is within 256kb, at the most it can go till 512kb > + > +/* > + * Default environment variables > + */ > +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ > + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ > + "${x_bootcmd_usb}; bootm 0x6400000;" > + > +#define MTDIDS_DEFAULT "nand0=nand_mtd" > +#define MTDPARTS_DEFAULT > "mtdparts=nand_mtd:0x100...@0x000000(uboot),0x400...@0x100000( > uImage),"\ > + "0x1fb00...@0x500000(rootfs)" This is must be the default setup in board setup file for openrd_base (if it is again derived from sheevaplug) In that case this settings not required > + > +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ > + "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ > + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ > + "x_bootcmd_usb=usb start\0" \ You must add x_bootcmd_eth for program MAC addrss in hardware before kernel boot. > + "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ > + "mtdids="MTDIDS_DEFAULT"\0" \ > + "mtdparts="MTDPARTS_DEFAULT"\0" > + > +/* > + * Size of malloc() pool > + */ > +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB > for malloc() */ > +/* size in bytes reserved for initial data */ > +#define CONFIG_SYS_GBL_DATA_SIZE 128 > + > +/* > + * Other required minimal configurations > + */ > +#define CONFIG_SYS_LONGHELP > +#define CONFIG_AUTO_COMPLETE > +#define CONFIG_CMDLINE_EDITING > +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ > +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ > +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ > +#define CONFIG_NR_DRAM_BANKS 4 > +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ > +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load > adr- 8M */ > +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ > +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ > +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ > + > +/* > + * Ethernet Driver configuration > + */ > +#ifdef CONFIG_CMD_NET > +#define CONFIG_NETCONSOLE /* include NetConsole support */ > +#define CONFIG_NET_MULTI /* specify more that one ports > available */ > +#define CONFIG_MII /* expose smi ove > miiphy interface */ > +#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe > Controller Driver */ > +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link > using phy */ > +#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */ > +#define CONFIG_PHY_BASE_ADR 0x8 > +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ > +#define CONFIG_RESET_PHY_R /* use reset_phy() to init > mv8831116 PHY */ > +#endif /* CONFIG_CMD_NET */ > + > +/* > + * USB/EHCI > + */ > +#ifdef CONFIG_CMD_USB > +#define CONFIG_USB_EHCI /* Enable EHCI > USB support */ > +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ > +#define CONFIG_EHCI_IS_TDI > +#define CONFIG_USB_STORAGE > +#define CONFIG_DOS_PARTITION > +#define CONFIG_ISO_PARTITION > +#define CONFIG_SUPPORT_VFAT > +#endif /* CONFIG_CMD_USB */ > + > +#endif /* _CONFIG_OPENRD_BASE_H */ > -- Regards.. Prafulla . . > 1.6.0.4 > > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
