Hi Mateusz,
On 10 December 2015 at 14:41, Mateusz Kulikowski
<mateusz.kulikow...@gmail.com> wrote:
> Add support for gpio controllers on Qualcomm Snapdragon devices.
> This devices are usually called Top Level Mode Multiplexing in
> Qualcomm documentation.
>
> Signed-off-by: Mateusz Kulikowski <mateusz.kulikow...@gmail.com>
> ---
>
> drivers/gpio/Kconfig | 7 +++
> drivers/gpio/Makefile | 2 +-
> drivers/gpio/msm_gpio.c | 115
> ++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 123 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpio/msm_gpio.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index e60e9fd..1d9443b 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -46,6 +46,13 @@ config LPC32XX_GPIO
> help
> Support for the LPC32XX GPIO driver.
>
> +config MSM_GPIO
> + bool "Qualcomm GPIO driver"
> + depends on DM_GPIO
> + default n
> + help
> + Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
Any more details? How many banks? How are they named? What features
does the driver support?
> +
> config ROCKCHIP_GPIO
> bool "Rockchip GPIO driver"
> depends on DM_GPIO
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index fb4fd25..9520b1e 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
> obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
> obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
> obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
> -
> +obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
> diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
> new file mode 100644
> index 0000000..9bb9e89
> --- /dev/null
> +++ b/drivers/gpio/msm_gpio.c
> @@ -0,0 +1,115 @@
> +/*
> + * Qualcomm GPIO driver
> + *
> + * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikow...@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <errno.h>
Put errno.h below dm.h
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct msm_gpio_bank {
> + phys_addr_t base;
> +};
> +
> +static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
> +{
> + struct msm_gpio_bank *priv = dev_get_priv(dev);
> + phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
> +
> + /* Disable OE bit */
> + writel((readl(reg) & ~GPIO_OE_MASK) | GPIO_OE_DISABLE , reg);
How about:
clrsetbits_le32(reg, GPIO_OE_MASK, GPIO_OE_DISABLE)
> + return 0;
> +}
> +
> +static int msm_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
> +{
> + struct msm_gpio_bank *priv = dev_get_priv(dev);
> +
> + value = !!value;
> + /* set value */
> + writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
> + return 0;
> +}
> +
> +static int msm_gpio_direction_output(struct udevice *dev, unsigned gpio,
> + int value)
> +{
> + struct msm_gpio_bank *priv = dev_get_priv(dev);
> + phys_addr_t reg = priv->base + GPIO_CONFIG_OFF(gpio);
> +
> + value = !!value;
> + /* set value */
> + writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_OFF(gpio));
> + /* switch direction */
> + writel((readl(reg) & ~GPIO_OE_MASK) | GPIO_OE_ENABLE , reg);
> + return 0;
> +}
> +
> +static int msm_gpio_get_value(struct udevice *dev, unsigned gpio)
> +{
> + struct msm_gpio_bank *priv = dev_get_priv(dev);
> +
> + return !!(readl(priv->base + GPIO_IN_OUT_OFF(gpio)) >> GPIO_IN);
> +}
> +
> +static int msm_gpio_get_function(struct udevice *dev, unsigned offset)
> +{
> + struct msm_gpio_bank *priv = dev_get_priv(dev);
> +
> + if (readl(priv->base + GPIO_CONFIG_OFF(offset)) & GPIO_OE_ENABLE)
> + return GPIOF_OUTPUT;
> + return GPIOF_INPUT;
> +}
> +
> +static const struct dm_gpio_ops gpio_msm_ops = {
> + .direction_input = msm_gpio_direction_input,
> + .direction_output = msm_gpio_direction_output,
> + .get_value = msm_gpio_get_value,
> + .set_value = msm_gpio_set_value,
> + .get_function = msm_gpio_get_function,
> +};
> +
> +static int msm_gpio_probe(struct udevice *dev)
> +{
> + struct msm_gpio_bank *priv = dev_get_priv(dev);
> +
> + priv->base = dev_get_addr(dev);
> + return priv->base == FDT_ADDR_T_NONE;
> +}
> +
> +static int msm_gpio_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +
> + uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
> + "gpio-count", 0);
> + uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
> + "gpio-bank-name", NULL);
> + if (uc_priv->bank_name == NULL)
> + uc_priv->bank_name = "soc";
> + return 0;
> +}
> +
> +static const struct udevice_id msm_gpio_ids[] = {
> + { .compatible = "qcom,msm8916-pinctrl" },
Is there a device binding tree binding file you can put in
doc/device-tree-bindings?
> + { }
> +};
> +
> +U_BOOT_DRIVER(gpio_msm) = {
> + .name = "gpio_msm",
> + .id = UCLASS_GPIO,
> + .of_match = msm_gpio_ids,
> + .ofdata_to_platdata = msm_gpio_ofdata_to_platdata,
> + .probe = msm_gpio_probe,
> + .ops = &gpio_msm_ops,
> + .priv_auto_alloc_size = sizeof(struct msm_gpio_bank),
> +};
> +
> +
> --
> 2.5.0
>
Regards,
Simon
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