On Tuesday, July 28, 2015 at 09:21:50 PM, Dinh Nguyen wrote: > On 7/27/15 3:49 PM, Marek Vasut wrote: > > The current bridge reset code, which de-asserted the bridge reset, > > was activelly polling whether the FPGA is programmed and ready and > > s/activelly/actively > > Again...only comment for this patch, no need to resend.
Fixed, thanks! Sorry about the blast of patches . How far are you with the review please? :) Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
