On 7/27/15 3:49 PM, Marek Vasut wrote: > The current bridge reset code, which de-asserted the bridge reset, > was activelly polling whether the FPGA is programmed and ready and
s/activelly/actively Again...only comment for this patch, no need to resend. Dinh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
