Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.
Signed-off-by: Marek Vasut <ma...@denx.de>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
arch/arm/mach-socfpga/reset_manager.c | 58 +++++++++++++---------
2 files changed, 37 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index fff4c96..56509c2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -12,6 +12,8 @@ void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_reset(int enable);
+void socfpga_per_reset(u32 reset, int set);
+
void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
void socfpga_spim_enable(void);
diff --git a/arch/arm/mach-socfpga/reset_manager.c
b/arch/arm/mach-socfpga/reset_manager.c
index 8ede779..452377c 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -15,16 +15,38 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+ const void *reg;
+
+ if (RSTMGR_BANK(reset) == 0)
+ reg = &reset_manager_base->mpu_mod_reset;
+ else if (RSTMGR_BANK(reset) == 1)
+ reg = &reset_manager_base->per_mod_reset;
+ else if (RSTMGR_BANK(reset) == 2)
+ reg = &reset_manager_base->per2_mod_reset;
+ else if (RSTMGR_BANK(reset) == 3)
+ reg = &reset_manager_base->brg_mod_reset;
+ else if (RSTMGR_BANK(reset) == 4)
+ reg = &reset_manager_base->misc_mod_reset;
+ else /* Invalid reset register, do nothing */
+ return;
+
+ if (set)
+ setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ else
+ clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
void socfpga_watchdog_reset(void)
{
/* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per_mod_reset,
- 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
/* deassert watchdog from reset (watchdog in not running state) */
- clrbits_le32(&reset_manager_base->per_mod_reset,
- 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
}
/*
@@ -91,16 +113,14 @@ void socfpga_bridges_reset(int enable)
/* Change the reset state for EMAC 0 and EMAC 1 */
void socfpga_emac_reset(int enable)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
if (enable) {
- setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
- setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
} else {
#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
#endif
}
}
@@ -108,32 +128,24 @@ void socfpga_emac_reset(int enable)
/* SPI Master enable (its held in reset by the preloader) */
void socfpga_spim_enable(void)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM0))) |
- (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM1))));
+ socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
+ socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
}
/* Bring UART0 out of reset. */
void socfpga_uart0_enable(void)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(UART0)));
+ socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
}
/* Bring SDRAM controller out of reset. */
void socfpga_sdram_enable(void)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(SDR)));
+ socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
}
/* Bring OSC1 timer out of reset. */
void socfpga_osc1timer_enable(void)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(OSC1TIMER0)));
+ socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
}
--
2.1.4
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