This patch adds support for the jadecpu board using the
MB86R01 'Jade' SoC from Fujitsu.
Signed-off-by: Matthias Weisser <matthias.weis...@graf-syteco.de>
---
MAINTAINERS | 4 +
MAKEALL | 1 +
Makefile | 7 +
board/syteco/jadecpu/Makefile | 55 ++++++
board/syteco/jadecpu/config.mk | 1 +
board/syteco/jadecpu/jadecpu.c | 99 ++++++++++
board/syteco/jadecpu/lowlevel_init.S | 337 ++++++++++++++++++++++++++++++++++
include/configs/jadecpu.h | 160 ++++++++++++++++
tools/Makefile | 3 +
tools/logos/syteco.bmp | Bin 0 -> 12278 bytes
10 files changed, 667 insertions(+), 0 deletions(-)
create mode 100644 board/syteco/jadecpu/Makefile
create mode 100644 board/syteco/jadecpu/config.mk
create mode 100644 board/syteco/jadecpu/jadecpu.c
create mode 100644 board/syteco/jadecpu/lowlevel_init.S
create mode 100644 include/configs/jadecpu.h
create mode 100644 tools/logos/syteco.bmp
diff --git a/MAINTAINERS b/MAINTAINERS
index 9379c7e..157f437
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -671,6 +671,10 @@ Sergey Lapin <sla...@ossfans.org>
afeb9260 ARM926EJS (AT91SAM9260 SoC)
+Matthias Weisser <matthias.weis...@graf-syteco.de>
+
+ jadecpu ARM926EJS (Jade SoC)
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/MAKEALL b/MAKEALL
index f4599d6..841c3d6
--- a/MAKEALL
+++ b/MAKEALL
@@ -533,6 +533,7 @@ LIST_ARM9=" \
davinci_sffsdr \
davinci_sonata \
davinci_dm355evm \
+ jadecpu \
"
#########################################################################
diff --git a/Makefile b/Makefile
index bcc81c9..0088d6d
--- a/Makefile
+++ b/Makefile
@@ -2785,6 +2785,13 @@ at91sam9rlek_config : unconfig
pm9263_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
+#########################################################################
+## Different ARM926EJ-S Systems
+#########################################################################
+
+jadecpu_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs jadecpu syteco jade
+
########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.
integratorap_config \
diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile
new file mode 100644
index 0000000..87d2234
--- /dev/null
+++ b/board/syteco/jadecpu/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian....@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += jadecpu.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk
new file mode 100644
index 0000000..c661f0b
--- /dev/null
+++ b/board/syteco/jadecpu/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x46000000
diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c
new file mode 100644
index 0000000..51dc8f7
--- /dev/null
+++ b/board/syteco/jadecpu/jadecpu.c
@@ -0,0 +1,99 @@
+/*
+ * (c) 2009 Graf-Syteco, Matthias Weisser
+ * <matthias.weis...@graf-syteco.de>
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <c...@mycable.de>, Alexander Bigga <a...@mycable.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/jade.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void multiplex_group_init(void);
+void gpio_init(void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+ printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* arch number of Versatile Board */
+ gd->bd->bi_arch_number = 0 /*MACH_TYPE_GSJADECPU*/;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x47000000;
+
+ gd->flags = 0;
+
+ icache_enable();
+
+ /* set Multiplex Group */
+ multiplex_group_init();
+
+ /* init GPIOs */
+ gpio_init();
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ setenv("verify", "n");
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+/*
+ * Initial the Pin Multiplex Groups
+ */
+void multiplex_group_init(void)
+{
+
+}
+
+void gpio_init(void)
+{
+
+}
+
diff --git a/board/syteco/jadecpu/lowlevel_init.S
b/board/syteco/jadecpu/lowlevel_init.S
new file mode 100644
index 0000000..727eda5
--- /dev/null
+++ b/board/syteco/jadecpu/lowlevel_init.S
@@ -0,0 +1,337 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <c...@mycable.de>, Alexander Bigga <a...@mycable.de>
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <c...@mycable.de>, Alexander Bigga <a...@mycable.de>
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.ro...@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software/* you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation/* either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY/* without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program/* if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+/*
+ * Initialize Clock Reset Generator (CRG)
+ */
+
+ ldr r0, =0xfffe7000 /* CRG base address */
+
+ /* Not change the initial value that is set by external pin.*/
+1: ldr r2, [r0, #0x00] /* Wait for PLLREADY */
+ tst r2, #0x00000100
+ beq 1b
+
+ /* Set clock gate control */
+ ldr r1, =0x0000ffff /* Open */
+ str r1, [r0, #0x18] /* CRHA: AHB clock */
+ ldr r1, =0x0000ffff /* Open */
+ str r1, [r0, #0x1c] /* CRPA: APB-A clock */
+ ldr r1, =0xfffffffe /* Close */
+ str r1, [r0, #0x20] /* CRPA: APB-B clock */
+ ldr r1, =0x0000ffff /* Open */
+ str r1, [r0, #0x24] /* CRHB: ExtAHB clock */
+ ldr r1, =0xffffffef /* Open ARM926EJ-S only */
+ str r1, [r0, #0x28] /* CRAM: ARM core clock */
+
+/*
+ * Initialize External Bus Interface
+ */
+#define MEMC_BASE 0xfffc0000
+
+ ldr r0, =MEMC_BASE /* MEMC base address */
+
+ /*
+ * SRAM/flash _mode_ registers (XCS4 is set by external pin)
+ * XCS0: Ethernet Controller
+ * XCS2: not used (?)
+ * XCS4: Flash
+ */
+ ldr r1, =0x00000001 /* XCS0: 16bit */
+ str r1, [r0, #0x00]
+ ldr r1, =0x00000001 /* XCS2: 16bit */
+ str r1, [r0, #0x08]
+ ldr r1, =0x00000021 /* XCS4: 16bit, */
+ str r1, [r0, #0x10]
+
+ /* SRAM/flash _timing_ registers (HCLK=83.3/80MHz) */
+ ldr r1, =0x055ff00f /* XCS0: */
+ str r1, [r0, #0x20]
+ ldr r1, =0x03061008 /* XCS2: not used */
+ str r1, [r0, #0x28]
+ ldr r1, =0x03061804 /* XCS4: FLASH ROM */
+ str r1, [r0, #0x30]
+
+ /* SRAM/flash _area_ registers (address of XCS4 is set by hardware) */
+ ldr r1, =0x00000020
+ str r1, [r0, #0x40]
+ ldr r1, =0x00000050 /* XCS2: 0x05000000/2MB */
+ str r1, [r0, #0x48]
+ ldr r1, =0x001f0000 /* XCS4: 32 MB */
+ str r1, [r0, #0x50]
+
+/*
+ * GPIO Settings
+ */
+
+/*
+ * Initialize DDR2 Controller
+ */
+#define CCNT_BASE 0xfff42000
+#define CDEBUG1 0xec
+
+#define DDR2C_BASE 0xf3000000
+#define DRIC 0x00
+#define DRIC1 0x02
+#define DRIC2 0x04
+#define DRCA 0x06
+#define DRCM 0x08
+#define DRCST1 0x0a
+#define DRCST2 0x0c
+#define DRCR 0x0e
+#define DRCF 0x20
+#define DRASR 0x30
+#define DRIMS 0x50
+#define DROS 0x60
+#define DRIBSLI 0x62
+#define DRIBSODT1 0x64
+#define DRIBSOCD 0x66
+#define DRIBSOCD2 0x68
+#define DROABA 0x70
+#define DROBV 0x80
+#define DROBS 0x84
+#define DROBSR1 0x86
+#define DROBSR2 0x88
+#define DROBSR3 0x8a
+#define DROBSR4 0x8c
+#define DRIMR1 0x90
+#define DRIMR2 0x92
+#define DRIMR3 0x94
+#define DRIMR4 0x96
+#define DROISR1 0x98
+#define DROISR2 0x9a
+
+ .macro wait, count
+ mov r4, #\count
+3:
+ subs r4, r4, #0x1
+ bne 3b
+
+ .endm
+
+ /* Wait for PLL LOCK up time or more */
+ wait 20
+
+ /*
+ * (2) Initialize DDRIF
+ */
+ ldr r0, =DDR2C_BASE /* DDR2C base address */
+ ldr r1, =0x5555
+ strh r1, [r0, #DRIMS]
+
+ /*
+ * (3) Wait for 20MCKPs(120nsec) or more
+ */
+ wait 20
+
+ /*
+ * (4) IRESET/IUSRRST release
+ /*
+ ldr r0, =CCNT_BASE /* CCNT base address */
+ ldr r1, =0x00000002
+ str r1, [r0, #CDEBUG1]
+
+ /*
+ * (5) Wait for 20MCKPs(120nsec) or more
+ */
+ wait 20
+
+ /*
+ * (6) IDLLRST release
+ */
+ ldr r0, =CCNT_BASE /* CCNT base address */
+ ldr r1, =0x00000003
+ str r1, [r0, #CDEBUG1]
+
+ /*
+ * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
+ */
+ wait 33536
+
+ /*
+ * (9) MCKE ON
+ */
+ ldr r0, =DDR2C_BASE /* DDR2C base address */
+ ldr r1, =0x003f
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0000
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc124 /* 512Mbit DDR2SDRAM x 2 */
+ strh r1, [r0, #DRCA]
+ ldr r1, =0xc000
+ strh r1, [r0, #DRIC]
+
+ /*
+ * (10) Initialize SDRAM
+ */
+ ldr r0, =DDR2C_BASE /* DDR2C base address */
+ ldr r1, =0xc001 /* NOP Command */
+ strh r1, [r0, #DRIC]
+
+ wait 67 /* 400ns wait */
+
+ ldr r1, =0x0017 /* PALL Command */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0400
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ ldr r1, =0x0006 /* EMR(2) command */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0000
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ ldr r1, =0x0007 /* EMR(3) command */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0000
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ ldr r1, =0x0005 /* EMR(1) command */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0000 /* Extended Mode Register 1 clear*/
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ ldr r1, =0x0004 /* MRS command */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0532 /* Mode Register */
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ wait 200
+
+ ldr r1, =0x0017 /* PALL command */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0400
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ ldr r1, =0x000f /* REF command 1 */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0000 /* (changed) */
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ wait 18 /* 105ns wait */
+
+ ldr r1, =0x0004 /* MRS command */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0432
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ wait 200 /* MRS to OCD: 200clock */
+
+ ldr r1, =0x0005 /* EMR(1) command */
+ strh r1, [r0, #DRIC1]
+ ldr r1, =0x0380 /* Extended Mode Register 1 set OCD */
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ ldr r1, =0x0005 /* EMR(1) command */
+ strh r1, [r0, #DRIC1]
+ /* ldr r1, =0x0044 */
+ ldr r1, =0x0002 /* EMR(1) set reduced strength */
+ strh r1, [r0, #DRIC2]
+ ldr r1, =0xc001
+ strh r1, [r0, #DRIC]
+
+ ldr r1, =0x0032 /* Set BT, AL, CL, BL */
+ strh r1, [r0, #DRCM]
+
+ ldr r1, =0x3418 /* Set tRCD, tRAS, tRP, tRC */
+ strh r1, [r0, #DRCST1]
+
+ /* ldr r1, =0x2e22 */ /* Set tRFC, tRRD, tWR */
+ ldr r1, =0x6e32
+ strh r1, [r0, #DRCST2]
+
+ /* ldr r1, =0x0051 */ /* Set CNTL, REF_CNT*/
+ ldr r1, =0x0141 /* (changed) */
+ strh r1, [r0, #DRCR]
+
+ ldr r1, =0x0002 /* Set Address FIFO (8 steps) */
+ strh r1, [r0, #DRCF]
+
+ ldr r1, =0x0001 /* Enable AXI Cache */
+ strh r1, [r0, #DRASR]
+
+ /*
+ * (11) ODT setting
+ */
+ ldr r0, =DDR2C_BASE /* DDR2C base address */
+ ldr r1, =0x0001
+ strh r1, [r0, #DROBS]
+ ldr r1, =0x0103 /* ODT auto adjustment on */
+ strh r1, [r0, #DROABA]
+ ldr r1, =0x003F /* Set ODT to on 50/100 Ohm */
+ strh r1, [r0, #DRIBSODT1]
+
+ /*
+ * (12) Shift to ODTCONT ON (SDRAM side) and DDR2C usual operation mode
+ */
+ ldr r0, =DDR2C_BASE /* DDR2C base address */
+ ldr r1, =0x0001
+ strh r1, [r0, #DROS]
+ ldr r1, =0x4000
+ strh r1, [r0, #DRIC]
+
+ mov pc, lr
+
+/*
+ * Reset CPU by writing SWRSTREQ to CRSR-register
+ */
+.globl reset_cpu
+reset_cpu:
+ ldr r0, =0xfffe7000 /* CRG Base address */
+ ldr r2, =0x00000002 /* SWRSTREQ */
+ str r2, [r0, #0x0c]
+
+_loop_forever:
+ b _loop_forever
+
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
new file mode 100644
index 0000000..235d0b6
--- /dev/null
+++ b/include/configs/jadecpu.h
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2007-2008
+ * Matthias Weisser <matthias.weis...@graf-syteco.de>
+ *
+ * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_JADE_IOCLK (41500000)
+#define CONFIG_SYS_TIMERBASE 0xfffe0000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * Serial
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_JADE_IOCLK
+#define CONFIG_SYS_NS16550_COM1 0xfffe1000
+#define CONFIG_SYS_NS16550_COM2 0xfffe2000
+
+#define CONFIG_CONS_INDEX 1
+
+/*
+ * Ethernet
+ */
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_BASE 0x02000000
+#define CONFIG_DRIVER_SMC911X_16_BIT
+
+/*
+ * Video
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_JADEGDC
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_LOGO
+#define VIDEO_KBD_INIT_FCT 0
+#define VIDEO_TSTC_FCT serial_tstc
+#define VIDEO_GETC_FCT serial_getc
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_IMI 1
+#define CONFIG_CMD_ELF 1
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_BMP 1
+/* #define CONFIG_CMD_USB 1 */
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */
+#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (128 * 1024)
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
+
+#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "jade> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)
+ 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_BOOTDELAY 2
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif /* __CONFIG_H */
+
diff --git a/tools/Makefile b/tools/Makefile
index 43c284c..456e9dd
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -125,6 +125,9 @@ endif
ifeq ($(VENDOR),ronetix)
LOGO_BMP= logos/ronetix.bmp
endif
+ifeq ($(VENDOR),syteco)
+LOGO_BMP= logos/syteco.bmp
+endif
# now $(obj) is defined
SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
diff --git a/tools/logos/syteco.bmp b/tools/logos/syteco.bmp
new file mode 100644
index
0000000000000000000000000000000000000000..141ee8e10edd85caa52b9501e3a4381b81fe772d
GIT binary patch
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literal 0
HcmV?d00001
--
1.5.6.3
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