This patch adds support for MB86R01 'Jade' SoC from Fujitsu
Signed-off-by: Matthias Weisser <matthias.weis...@graf-syteco.de>
---
cpu/arm926ejs/jade/Makefile | 47 +++++++++
cpu/arm926ejs/jade/timer.c | 126 ++++++++++++++++++++++++
include/asm-arm/arch-jade/hardware.h | 31 ++++++
include/asm-arm/arch-jade/jade.h | 177 ++++++++++++++++++++++++++++++++++
4 files changed, 381 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm926ejs/jade/Makefile
create mode 100644 cpu/arm926ejs/jade/timer.c
create mode 100644 include/asm-arm/arch-jade/hardware.h
create mode 100644 include/asm-arm/arch-jade/jade.h
diff --git a/cpu/arm926ejs/jade/Makefile b/cpu/arm926ejs/jade/Makefile
new file mode 100644
index 0000000..7da9f40
--- /dev/null
+++ b/cpu/arm926ejs/jade/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = timer.o
+SOBJS =
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/jade/timer.c b/cpu/arm926ejs/jade/timer.c
new file mode 100644
index 0000000..2d262c8
--- /dev/null
+++ b/cpu/arm926ejs/jade/timer.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian....@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Matthias Weisser <matthias.weis...@graf-syteco.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_BASE 0xfffe0000
+
+#define READ_TIMER (*(volatile ulong *)(TIMER_BASE+4))
+#define TIMER_FREQ (CONFIG_JADE_IOCLK / 16)
+
+static ulong timestamp;
+static ulong lastdec;
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, TIMER_FREQ);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= TIMER_FREQ;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+ *(volatile ulong *)(TIMER_BASE + 0) = TIMER_LOAD_VAL;
+ *(volatile ulong *)(TIMER_BASE + 8) = 0x86;
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+ ulong now = READ_TIMER;
+
+ if (now <= lastdec) /* normal mode (non roll) */
+ /* move stamp forward with absolut diff ticks */
+ timestamp += (lastdec - now);
+ else /* we have rollover of incrementer */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ lastdec = now;
+ return timestamp;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER; /* capture current decrement value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+void udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = usec_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ ulong tbclk;
+
+ tbclk = CONFIG_SYS_HZ;
+ return tbclk;
+}
diff --git a/include/asm-arm/arch-jade/hardware.h
b/include/asm-arm/arch-jade/hardware.h
new file mode 100644
index 0000000..a26bdca
--- /dev/null
+++ b/include/asm-arm/arch-jade/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ * <c...@mycable.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <asm/arch/jade.h>
+
+#endif
diff --git a/include/asm-arm/arch-jade/jade.h b/include/asm-arm/arch-jade/jade.h
new file mode 100644
index 0000000..c2b28a2
--- /dev/null
+++ b/include/asm-arm/arch-jade/jade.h
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2007
+ *
+ * jade definitions
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ * <c...@mycable.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef JADE_H
+#define JADE_H
+
+typedef volatile unsigned int JREG; /* Hardware register */
+
+/*
+ * Physical Address Defines
+ */
+#define JADE_GDC_PHYS_BASE 0xf1fc0000
+#define JADE_GDC_PHYS_DISP_BASE 0xf1fd0000
+#define JADE_CCNT_PHYS_BASE 0xfff42000
+#define JADE_CAN0_PHYS_BASE 0xfff54000
+#define JADE_CAN1_PHYS_BASE 0xfff55000
+#define JADE_I2C0_PHYS_BASE 0xfff56000
+#define JADE_I2C1_PHYS_BASE 0xfff57000
+#define JADE_EHCI_PHYS_BASE 0xfff80000
+#define JADE_OHCI_PHYS_BASE 0xfff81000
+#define JADE_IRC1_PHYS_BASE 0xfffb0000
+#define JADE_TIMER_PHYS_BASE 0xfffe0000
+#define JADE_UART0_PHYS_BASE 0xfffe1000
+#define JADE_UART1_PHYS_BASE 0xfffe2000
+#define JADE_IRCE_PHYS_BASE 0xfffe4000
+#define JADE_CRG_PHYS_BASE 0xfffe7000
+#define JADE_IRC0_PHYS_BASE 0xfffe8000
+#define JADE_GPIO_PHYS_BASE 0xfffe9000
+
+
+/* DRAMC_DRIC DRAM Controller Mode Register */
+
+/*
+ * REGISTER ADDRESS DEFINITION FOR DRAMC PERIPHERAL
+ */
+#define JREGC_DRAMC_DRIC ((JREG *) 0xF3000000)
+#define JREGC_DRAMC_DRIC1 ((JREG *) 0xF3000002)
+#define JREGC_DRAMC_DRIC2 ((JREG *) 0xF3000004)
+#define JREGC_DRAMC_DRCA ((JREG *) 0xF3000006)
+#define JREGC_DRAMC_DRCM ((JREG *) 0xF3000008)
+#define JREGC_DRAMC_DRCST1 ((JREG *) 0xF300000A)
+#define JREGC_DRAMC_DRCST2 ((JREG *) 0xF300000C)
+#define JREGC_DRAMC_DRCR ((JREG *) 0xF300000E)
+#define JREGC_DRAMC_DRCS ((JREG *) 0xF3000020)
+#define JREGC_DRAMC_DRASR ((JREG *) 0xF3000030)
+#define JREGC_DRAMC_DRIMS1 ((JREG *) 0xF3000042)
+#define JREGC_DRAMC_DRIMS2A1 ((JREG *) 0xF3000044)
+#define JREGC_DRAMC_DRIMS3A2 ((JREG *) 0xF3000046)
+#define JREGC_DRAMC_DRIMS4 ((JREG *) 0xF3000048)
+#define JREGC_DRAMC_DRIMS5 ((JREG *) 0xF300004A)
+#define JREGC_DRAMC_DRIMS6 ((JREG *) 0xF300004C)
+#define JREGC_DRAMC_DRIMS7D1 ((JREG *) 0xF300004E)
+#define JREGC_DRAMC_DRIMS8D2 ((JREG *) 0xF3000050)
+#define JREGC_DRAMC_DRIMS9T1 ((JREG *) 0xF3000052)
+#define JREGC_DRAMC_DRIMSS10T2 ((JREG *) 0xF3000054)
+#define JREGC_DRAMC_DROS ((JREG *) 0xF3000060)
+#define JREGC_DRAMC_DRIBSLI ((JREG *) 0xF3000062)
+#define JREGC_DRAMC_DRIBSODT1 ((JREG *) 0xF3000064)
+#define JREGC_DRAMC_DRIBSOCD ((JREG *) 0xF3000066)
+#define JREGC_DRAMC_DRIBSOCD2 ((JREG *) 0xF3000068)
+#define JREGC_DRAMC_DROABA ((JREG *) 0xF3000070)
+#define JREGC_DRAMC_DROBV ((JREG *) 0xF3000080)
+#define JREGC_DRAMC_DROBS ((JREG *) 0xF3000084)
+#define JREGC_DRAMC_DROBSR1 ((JREG *) 0xF3000086)
+#define JREGC_DRAMC_DROBSR2 ((JREG *) 0xF3000088)
+#define JREGC_DRAMC_DROBSR3 ((JREG *) 0xF300008A)
+#define JREGC_DRAMC_DROBSR4 ((JREG *) 0xF300008C)
+#define JREGC_DRAMC_DRIMR1 ((JREG *) 0xF3000090)
+#define JREGC_DRAMC_DRIMR2 ((JREG *) 0xF3000092)
+#define JREGC_DRAMC_DRIMR3 ((JREG *) 0xF3000094)
+#define JREGC_DRAMC_DRIMR4 ((JREG *) 0xF3000096)
+#define JREGC_DRAMC_DROISR1 ((JREG *) 0xF3000098)
+#define JREGC_DRAMC_DROISR2 ((JREG *) 0xF300009A)
+
+/*
+ * REGISTER ADDRESS DEFINITION FOR GPIO PERIPHERAL
+ */
+/* GPIO Port data register */
+#define GPIO_PORT_DATA 0x00
+/* GPIO Data Direction */
+#define GPIO_DIRECTION 0x10
+
+/* GPIO Block Defines */
+#define GPIO_BLOCK_0 0x00
+#define GPIO_BLOCK_1 0x04
+#define GPIO_BLOCK_2 0x08
+
+/*
+ * JADE Chip Control Module
+ *
+ */
+
+#define CCNT_CGPIO_IST 0x18
+#define CCNT_CGPIO_ISTM 0x1c
+#define CCNT_CGPIO_IP 0x20
+#define CCNT_CGPIO_IM 0x24
+#define CCNT_CMUX_MD 0x30
+
+/*
+ * REGISTER ADDRESS DEFINITION FOR UART0 PERIPHERAL
+ *
+#define JREGC_UART0_URT0RFR ((JREG *) 0xFFFE1000)
+#define JREGC_UART0_URT0TFR ((JREG *) 0xFFFE1000)
+#define JREGC_UART0_URT0DLL ((JREG *) 0xFFFE1000)
+#define JREGC_UART0_URT0IER ((JREG *) 0xFFFE1004)
+#define JREGC_UART0_URT0DLM ((JREG *) 0xFFFE1004)
+#define JREGC_UART0_URT0IIR ((JREG *) 0xFFFE1008)
+#define JREGC_UART0_URT0FCR ((JREG *) 0xFFFE1008)
+#define JREGC_UART0_URT0LCR ((JREG *) 0xFFFE100C)
+#define JREGC_UART0_URT0MCR ((JREG *) 0xFFFE1010)
+#define JREGC_UART0_URT0LSR ((JREG *) 0xFFFE1014)
+#define JREGC_UART0_URT0MSR ((JREG *) 0xFFFE1018)
+#define JREGC_UART0_URT0SCR ((JREG *) 0xFFFE101C)
+
+/*
+ * REGISTER ADDRESS DEFINITION FOR UART1 PERIPHERAL
+ */
+#define JREGC_UART1_URT1RFR ((JREG *) 0xFFFE2000)
+#define JREGC_UART1_URT1TFR ((JREG *) 0xFFFE2000)
+#define JREGC_UART1_URT1DLL ((JREG *) 0xFFFE2000)
+#define JREGC_UART1_URT1IER ((JREG *) 0xFFFE2004)
+#define JREGC_UART1_URT1DLM ((JREG *) 0xFFFE2004)
+#define JREGC_UART1_URT1IIR ((JREG *) 0xFFFE2008)
+#define JREGC_UART1_URT1FCR ((JREG *) 0xFFFE2008)
+#define JREGC_UART1_URT1LCR ((JREG *) 0xFFFE200C)
+#define JREGC_UART1_URT1MCR ((JREG *) 0xFFFE2010)
+#define JREGC_UART1_URT1LSR ((JREG *) 0xFFFE2014)
+#define JREGC_UART1_URT1MSR ((JREG *) 0xFFFE2018)
+#define JREGC_UART1_URT1SCR ((JREG *) 0xFFFE201C)
+
+/*
+ * REGISTER ADDRESS DEFINITION FOR CLOCK/RESET INTERFACE
+ */
+#define JREGC_CRG_CRPR ((JREG *) 0xFFFE7000)
+#define JREGC_CRG_CRWR ((JREG *) 0xFFFE7008)
+#define JREGC_CRG_CRSR ((JREG *) 0xFFFE700C)
+#define JREGC_CRG_CRDA ((JREG *) 0xFFFE7010)
+#define JREGC_CRG_CRDB ((JREG *) 0xFFFE7014)
+#define JREGC_CRG_CRHA ((JREG *) 0xFFFE7018)
+#define JREGC_CRG_CRPA ((JREG *) 0xFFFE701C)
+#define JREGC_CRG_CRPB ((JREG *) 0xFFFE7020)
+#define JREGC_CRG_CRHB ((JREG *) 0xFFFE7024)
+#define JREGC_CRG_CRAM ((JREG *) 0xFFFE7028)
+
+/*
+ * REGISTER BASE ADDRESS DEFINITION FOR PERIPHERAL
+ */
+#define JREGC_BASE_DRAM ((JREGPS_DRAMC) 0xF3000000)
+#define JREGC_BASE_GPIO ((JREGPS_GPIO) 0xFFFE9000)
+#define JREGC_BASE_UART0 ((JREGPS_UART0) 0xFFFE1000)
+#define JREGC_BASE_UART1 ((JREGPS_UART1) 0xFFFE2000)
+
+#endif /* jade_H */
--
1.5.6.3
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