This is an attempt at using a macro to allow mx6dl-ddr.h and
mx6q-ddr.h registers to be used together which is needed for an SPL bootloader
that can run on either CPU's and must configure MMDC iomux dynamically.
I am trying to come up with a solution similar to Eric's approach with the
similar issue regarding IMX pinmux but this approach is broken in that imximage
will choke on the cfgtmp file due to the fact that the pre-processor won't
use the enum's as it did the #defines. I'm looking for some positive
suggestions here or perhaps someone else can come up with a solution for this
particular issue which I haven't been able to resolve.
Signed-off-by: Tim Harvey <thar...@gateworks.com>
---
arch/arm/include/asm/arch-mx6/mx6-ddr.h | 29 +++++++++--
arch/arm/include/asm/arch-mx6/mx6dl-ddr.h | 82 ++++++++++++++++---------------
arch/arm/include/asm/arch-mx6/mx6q-ddr.h | 82 ++++++++++++++++---------------
3 files changed, 108 insertions(+), 85 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 43d377a..6ac857e 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -6,15 +6,34 @@
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
-#ifdef CONFIG_MX6Q
+#define MX6_ADDR_DECLARE(prefix, name, addr) \
+ prefix##name = addr
+
+#ifdef CONFIG_MX6QDL
+enum {
+#define MX6_ADDR_DECL(name, addr) \
+ MX6_ADDR_DECLARE(MX6Q_, name, addr),
#include "mx6q-ddr.h"
-#else
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+};
+#undef MX6_ADDR_DECL
+
+enum {
+#define MX6_ADDR_DECL(name, addr) \
+ MX6_ADDR_DECLARE(MX6DL_, name, addr),
+#include "mx6dl-ddr.h"
+};
+
+#elif defined(CONFIG_MX6Q)
+#define MX6_ADDR_DECL(name, addr) \
+ MX6_ADDR_DECLARE(MX6_, name, addr),
+#include "mx6q-ddr.h"
+#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#define MX6_ADDR_DECL(name, addr) \
+ MX6_ADDR_DECLARE(MX6_, name, addr),
#include "mx6dl-ddr.h"
#else
#error "Please select cpu"
-#endif /* CONFIG_MX6DL or CONFIG_MX6S */
-#endif /* CONFIG_MX6Q */
+#endif
#define MX6_MMDC_P0_MDCTL 0x021b0000
#define MX6_MMDC_P0_MDPDC 0x021b0004
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
index 1eb4b3c..4828974 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
@@ -6,54 +6,56 @@
#ifndef __ASM_ARCH_MX6DLS_DDR_H__
#define __ASM_ARCH_MX6DLS_DDR_H__
+#ifndef CONFIG_MX6QDL
#ifndef CONFIG_MX6DL
#ifndef CONFIG_MX6S
#error "wrong CPU"
#endif
#endif
+#endif
-#define MX6_IOM_DRAM_DQM0 0x020e0470
-#define MX6_IOM_DRAM_DQM1 0x020e0474
-#define MX6_IOM_DRAM_DQM2 0x020e0478
-#define MX6_IOM_DRAM_DQM3 0x020e047c
-#define MX6_IOM_DRAM_DQM4 0x020e0480
-#define MX6_IOM_DRAM_DQM5 0x020e0484
-#define MX6_IOM_DRAM_DQM6 0x020e0488
-#define MX6_IOM_DRAM_DQM7 0x020e048c
+MX6_ADDR_DECL(IOM_DRAM_DQM0, 0x020e0470)
+MX6_ADDR_DECL(IOM_DRAM_DQM1, 0x020e0474)
+MX6_ADDR_DECL(IOM_DRAM_DQM2, 0x020e0478)
+MX6_ADDR_DECL(IOM_DRAM_DQM3, 0x020e047c)
+MX6_ADDR_DECL(IOM_DRAM_DQM4, 0x020e0480)
+MX6_ADDR_DECL(IOM_DRAM_DQM5, 0x020e0484)
+MX6_ADDR_DECL(IOM_DRAM_DQM6, 0x020e0488)
+MX6_ADDR_DECL(IOM_DRAM_DQM7, 0x020e048c)
-#define MX6_IOM_DRAM_CAS 0x020e0464
-#define MX6_IOM_DRAM_RAS 0x020e0490
-#define MX6_IOM_DRAM_RESET 0x020e0494
-#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
-#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
-#define MX6_IOM_DRAM_SDBA2 0x020e04a0
-#define MX6_IOM_DRAM_SDCKE0 0x020e04a4
-#define MX6_IOM_DRAM_SDCKE1 0x020e04a8
-#define MX6_IOM_DRAM_SDODT0 0x020e04b4
-#define MX6_IOM_DRAM_SDODT1 0x020e04b8
+MX6_ADDR_DECL(IOM_DRAM_CAS, 0x020e0464)
+MX6_ADDR_DECL(IOM_DRAM_RAS, 0x020e0490)
+MX6_ADDR_DECL(IOM_DRAM_RESET, 0x020e0494)
+MX6_ADDR_DECL(IOM_DRAM_SDCLK_0, 0x020e04ac)
+MX6_ADDR_DECL(IOM_DRAM_SDCLK_1, 0x020e04b0)
+MX6_ADDR_DECL(IOM_DRAM_SDBA2, 0x020e04a0)
+MX6_ADDR_DECL(IOM_DRAM_SDCKE0, 0x020e04a4)
+MX6_ADDR_DECL(IOM_DRAM_SDCKE1, 0x020e04a8)
+MX6_ADDR_DECL(IOM_DRAM_SDODT0, 0x020e04b4)
+MX6_ADDR_DECL(IOM_DRAM_SDODT1, 0x020e04b8)
-#define MX6_IOM_DRAM_SDQS0 0x020e04bc
-#define MX6_IOM_DRAM_SDQS1 0x020e04c0
-#define MX6_IOM_DRAM_SDQS2 0x020e04c4
-#define MX6_IOM_DRAM_SDQS3 0x020e04c8
-#define MX6_IOM_DRAM_SDQS4 0x020e04cc
-#define MX6_IOM_DRAM_SDQS5 0x020e04d0
-#define MX6_IOM_DRAM_SDQS6 0x020e04d4
-#define MX6_IOM_DRAM_SDQS7 0x020e04d8
+MX6_ADDR_DECL(IOM_DRAM_SDQS0, 0x020e04bc)
+MX6_ADDR_DECL(IOM_DRAM_SDQS1, 0x020e04c0)
+MX6_ADDR_DECL(IOM_DRAM_SDQS2, 0x020e04c4)
+MX6_ADDR_DECL(IOM_DRAM_SDQS3, 0x020e04c8)
+MX6_ADDR_DECL(IOM_DRAM_SDQS4, 0x020e04cc)
+MX6_ADDR_DECL(IOM_DRAM_SDQS5, 0x020e04d0)
+MX6_ADDR_DECL(IOM_DRAM_SDQS6, 0x020e04d4)
+MX6_ADDR_DECL(IOM_DRAM_SDQS7, 0x020e04d8)
-#define MX6_IOM_GRP_B0DS 0x020e0764
-#define MX6_IOM_GRP_B1DS 0x020e0770
-#define MX6_IOM_GRP_B2DS 0x020e0778
-#define MX6_IOM_GRP_B3DS 0x020e077c
-#define MX6_IOM_GRP_B4DS 0x020e0780
-#define MX6_IOM_GRP_B5DS 0x020e0784
-#define MX6_IOM_GRP_B6DS 0x020e078c
-#define MX6_IOM_GRP_B7DS 0x020e0748
-#define MX6_IOM_GRP_ADDDS 0x020e074c
-#define MX6_IOM_DDRMODE_CTL 0x020e0750
-#define MX6_IOM_GRP_DDRPKE 0x020e0754
-#define MX6_IOM_GRP_DDRMODE 0x020e0760
-#define MX6_IOM_GRP_CTLDS 0x020e076c
-#define MX6_IOM_GRP_DDR_TYPE 0x020e0774
+MX6_ADDR_DECL(IOM_GRP_B0DS, 0x020e0764)
+MX6_ADDR_DECL(IOM_GRP_B1DS, 0x020e0770)
+MX6_ADDR_DECL(IOM_GRP_B2DS, 0x020e0778)
+MX6_ADDR_DECL(IOM_GRP_B3DS, 0x020e077c)
+MX6_ADDR_DECL(IOM_GRP_B4DS, 0x020e0780)
+MX6_ADDR_DECL(IOM_GRP_B5DS, 0x020e0784)
+MX6_ADDR_DECL(IOM_GRP_B6DS, 0x020e078c)
+MX6_ADDR_DECL(IOM_GRP_B7DS, 0x020e0748)
+MX6_ADDR_DECL(IOM_GRP_ADDDS, 0x020e074c)
+MX6_ADDR_DECL(IOM_DDRMODE_CTL, 0x020e0750)
+MX6_ADDR_DECL(IOM_GRP_DDRPKE, 0x020e0754)
+MX6_ADDR_DECL(IOM_GRP_DDRMODE, 0x020e0760)
+MX6_ADDR_DECL(IOM_GRP_CTLDS, 0x020e076c)
+MX6_ADDR_DECL(IOM_GRP_DDR_TYPE, 0x020e0774)
#endif /*__ASM_ARCH_MX6S_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
index 0aa94cf..bd9cf1a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
@@ -6,52 +6,54 @@
#ifndef __ASM_ARCH_MX6Q_DDR_H__
#define __ASM_ARCH_MX6Q_DDR_H__
+#ifndef CONFIG_MX6QDL
#ifndef CONFIG_MX6Q
#error "wrong CPU"
#endif
+#endif
-#define MX6_IOM_DRAM_DQM0 0x020e05ac
-#define MX6_IOM_DRAM_DQM1 0x020e05b4
-#define MX6_IOM_DRAM_DQM2 0x020e0528
-#define MX6_IOM_DRAM_DQM3 0x020e0520
-#define MX6_IOM_DRAM_DQM4 0x020e0514
-#define MX6_IOM_DRAM_DQM5 0x020e0510
-#define MX6_IOM_DRAM_DQM6 0x020e05bc
-#define MX6_IOM_DRAM_DQM7 0x020e05c4
+MX6_ADDR_DECL(IOM_DRAM_DQM0, 0x020e05ac)
+MX6_ADDR_DECL(IOM_DRAM_DQM1, 0x020e05b4)
+MX6_ADDR_DECL(IOM_DRAM_DQM2, 0x020e0528)
+MX6_ADDR_DECL(IOM_DRAM_DQM3, 0x020e0520)
+MX6_ADDR_DECL(IOM_DRAM_DQM4, 0x020e0514)
+MX6_ADDR_DECL(IOM_DRAM_DQM5, 0x020e0510)
+MX6_ADDR_DECL(IOM_DRAM_DQM6, 0x020e05bc)
+MX6_ADDR_DECL(IOM_DRAM_DQM7, 0x020e05c4)
-#define MX6_IOM_DRAM_CAS 0x020e056c
-#define MX6_IOM_DRAM_RAS 0x020e0578
-#define MX6_IOM_DRAM_RESET 0x020e057c
-#define MX6_IOM_DRAM_SDCLK_0 0x020e0588
-#define MX6_IOM_DRAM_SDCLK_1 0x020e0594
-#define MX6_IOM_DRAM_SDBA2 0x020e058c
-#define MX6_IOM_DRAM_SDCKE0 0x020e0590
-#define MX6_IOM_DRAM_SDCKE1 0x020e0598
-#define MX6_IOM_DRAM_SDODT0 0x020e059c
-#define MX6_IOM_DRAM_SDODT1 0x020e05a0
+MX6_ADDR_DECL(IOM_DRAM_CAS, 0x020e056c)
+MX6_ADDR_DECL(IOM_DRAM_RAS, 0x020e0578)
+MX6_ADDR_DECL(IOM_DRAM_RESET, 0x020e057c)
+MX6_ADDR_DECL(IOM_DRAM_SDCLK_0, 0x020e0588)
+MX6_ADDR_DECL(IOM_DRAM_SDCLK_1, 0x020e0594)
+MX6_ADDR_DECL(IOM_DRAM_SDBA2, 0x020e058c)
+MX6_ADDR_DECL(IOM_DRAM_SDCKE0, 0x020e0590)
+MX6_ADDR_DECL(IOM_DRAM_SDCKE1, 0x020e0598)
+MX6_ADDR_DECL(IOM_DRAM_SDODT0, 0x020e059c)
+MX6_ADDR_DECL(IOM_DRAM_SDODT1, 0x020e05a0)
-#define MX6_IOM_DRAM_SDQS0 0x020e05a8
-#define MX6_IOM_DRAM_SDQS1 0x020e05b0
-#define MX6_IOM_DRAM_SDQS2 0x020e0524
-#define MX6_IOM_DRAM_SDQS3 0x020e051c
-#define MX6_IOM_DRAM_SDQS4 0x020e0518
-#define MX6_IOM_DRAM_SDQS5 0x020e050c
-#define MX6_IOM_DRAM_SDQS6 0x020e05b8
-#define MX6_IOM_DRAM_SDQS7 0x020e05c0
+MX6_ADDR_DECL(IOM_DRAM_SDQS0, 0x020e05a8)
+MX6_ADDR_DECL(IOM_DRAM_SDQS1, 0x020e05b0)
+MX6_ADDR_DECL(IOM_DRAM_SDQS2, 0x020e0524)
+MX6_ADDR_DECL(IOM_DRAM_SDQS3, 0x020e051c)
+MX6_ADDR_DECL(IOM_DRAM_SDQS4, 0x020e0518)
+MX6_ADDR_DECL(IOM_DRAM_SDQS5, 0x020e050c)
+MX6_ADDR_DECL(IOM_DRAM_SDQS6, 0x020e05b8)
+MX6_ADDR_DECL(IOM_DRAM_SDQS7, 0x020e05c0)
-#define MX6_IOM_GRP_B0DS 0x020e0784
-#define MX6_IOM_GRP_B1DS 0x020e0788
-#define MX6_IOM_GRP_B2DS 0x020e0794
-#define MX6_IOM_GRP_B3DS 0x020e079c
-#define MX6_IOM_GRP_B4DS 0x020e07a0
-#define MX6_IOM_GRP_B5DS 0x020e07a4
-#define MX6_IOM_GRP_B6DS 0x020e07a8
-#define MX6_IOM_GRP_B7DS 0x020e0748
-#define MX6_IOM_GRP_ADDDS 0x020e074c
-#define MX6_IOM_DDRMODE_CTL 0x020e0750
-#define MX6_IOM_GRP_DDRPKE 0x020e0758
-#define MX6_IOM_GRP_DDRMODE 0x020e0774
-#define MX6_IOM_GRP_CTLDS 0x020e078c
-#define MX6_IOM_GRP_DDR_TYPE 0x020e0798
+MX6_ADDR_DECL(IOM_GRP_B0DS, 0x020e0784)
+MX6_ADDR_DECL(IOM_GRP_B1DS, 0x020e0788)
+MX6_ADDR_DECL(IOM_GRP_B2DS, 0x020e0794)
+MX6_ADDR_DECL(IOM_GRP_B3DS, 0x020e079c)
+MX6_ADDR_DECL(IOM_GRP_B4DS, 0x020e07a0)
+MX6_ADDR_DECL(IOM_GRP_B5DS, 0x020e07a4)
+MX6_ADDR_DECL(IOM_GRP_B6DS, 0x020e07a8)
+MX6_ADDR_DECL(IOM_GRP_B7DS, 0x020e0748)
+MX6_ADDR_DECL(IOM_GRP_ADDDS, 0x020e074c)
+MX6_ADDR_DECL(IOM_DDRMODE_CTL, 0x020e0750)
+MX6_ADDR_DECL(IOM_GRP_DDRPKE, 0x020e0758)
+MX6_ADDR_DECL(IOM_GRP_DDRMODE, 0x020e0774)
+MX6_ADDR_DECL(IOM_GRP_CTLDS, 0x020e078c)
+MX6_ADDR_DECL(IOM_GRP_DDR_TYPE, 0x020e0798)
#endif /*__ASM_ARCH_MX6Q_DDR_H__ */
--
1.8.3.2
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