On Fri, Jan 21, 2011 at 11:59:48AM -0500, der Mouse wrote:
> > m68010 doesn't have a real cache, but the very small instruction
> > fetch fifo is blocked when a djnz is executed, so that a very short
> > loop (1 other instruction) can be executed without repeated
> > instruction fetches.
>
> Reminds me of the KA630 (one of the MicroVAX-II CPU boards). I was
> building an emulator for it and it crashed in the ROM code. Turns out
> there's an instruction prefetch buffer. Most ways of doing control
> transfers flush it when appropriate. But turning on the MMU does _not_
> flush it; the ROM code turns on the MMU and then executes a handful of
> instructions out of the prefetch buffer, the last one being a jump to
> the same code at its now-MMU-mapped address.
>
> The VAX OS sources I have make sure that the MMU is set up so the same
> addresses work for physical and virtual before turning the MMU on,
> perhaps because different VAXen differ in this regard. But ROM code
> can assume it's running on the hardware it's for.
I made by arm board jump to an alias of it's ROM address so that when
the mmu was enabled (and the RAM put at zero - which was the nominal
addess of the ROM) the addresses memory wouldn't change.
Much more effective that doing a 'dance of death' through another
set of page tables.
David
--
David Laight: da...@l8s.co.uk
