> >> I see there is a compile time constant CACHE_LINE_SIZE in > >> <sys/param.h> which currently seems to be always be set to 64, but > >> I'm pretty certain that is not necessarily a correct value. > > > > You are correct; to cite the one example I currently have swapped into > > my brain, the Super-H used in the Dreamcast has 32-byte cache lines > > (true of the I-cache and D-cache both). > > I'm curious why non-kernel components would care.
i'd guess it's all for performance reasons. > The question also gets amusing when the cache line size varies among > the caches. That's not all that common, but it certainly happens. like on sparc64: cpu0 at mainbus0: SUNW,UltraSPARC-IIIi @ 1280 MHz, UPA id 0 cpu0: 32K instruction (32 b/l), 64K data (32 b/l), 1024K external (64 b/l) .mrg.
