On Jan 20, 2011, at 3:06 PM, Peter Seebach wrote:
> In message <145c3ac8-317e-4d8b-b696-19824a6b8...@dell.com>, Paul Koning
> writes:
>> On Jan 20, 2011, at 2:47 PM, der Mouse wrote:
>>>> I see there is a compile time constant CACHE_LINE_SIZE in
>>>> <sys/param.h> which currently seems to be always be set to 64, but
>>>> I'm pretty certain that is not necessarily a correct value.
>
>>> You are correct; to cite the one example I currently have swapped into
>>> my brain, the Super-H used in the Dreamcast has 32-byte cache lines
>>> (true of the I-cache and D-cache both).
>
>> I'm curious why non-kernel components would care.
>
> Look at the output of lmbench. Empirically, there are real-world performance
> effects in some boundary cases.
>
> Some people care about performance enough to tune for stuff like this.
Ok. So I guess what's really needed is the ability to ask about the cache
structure: levels, sizes, line sizes... the "config" registers in the MIPS
coprocessor zero make a nice example.
paul
