> m68010 doesn't have a real cache, but the very small instruction > fetch fifo is blocked when a djnz is executed, so that a very short > loop (1 other instruction) can be executed without repeated > instruction fetches.
Reminds me of the KA630 (one of the MicroVAX-II CPU boards). I was building an emulator for it and it crashed in the ROM code. Turns out there's an instruction prefetch buffer. Most ways of doing control transfers flush it when appropriate. But turning on the MMU does _not_ flush it; the ROM code turns on the MMU and then executes a handful of instructions out of the prefetch buffer, the last one being a jump to the same code at its now-MMU-mapped address. The VAX OS sources I have make sure that the MMU is set up so the same addresses work for physical and virtual before turning the MMU on, perhaps because different VAXen differ in this regard. But ROM code can assume it's running on the hardware it's for. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mo...@rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B
