Is there documentation that declares which simulations are not supported by
xsim? I have used build.py to produce modules.json. I also found a git
issue that states the qsfp wrapper simulation is not supported for xsim.
Can you provide any details on the system verilog constructs that are
utilize
Wade,
Thank you very much for the detailed explanation.
On Fri, Nov 1, 2024 at 10:35 AM Wade Fife wrote:
> Hi Andrew,
>
> This is true of all RFNoC images. The "ctrl" setting refers to whether or
> not that endpoint has a connection to the control crossbar, which is used
> for sending control p
I am investigating chopping a signal with a fast track and hold to bring a
microwave signal to baseband without relying on a mixer (I can explain why
if needed but I'll skip this background part for the moment).
To achieve this result I would like to fit a BasicRX board installed in a X310
wit
On 20/12/2024 13:44, frie...@free.fr wrote:
I am investigating chopping a signal with a fast track and hold to bring a
microwave signal to baseband without relying on a mixer (I can explain why
if needed but I'll skip this background part for the moment).
To achieve this result I would like to f
Hi Andrew,
All of the testbenches that have a Makefile should work with XSim except
for the ones listed in this file:
https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/tools/utils/testbenches.excludes
And all of the testbenches that have a Makefile should work in ModelSim
except for the
RFNoC 4 tries to do this automatically at the start of a session. When UHD
initializes a block, it will try to flush all of its FIFOs to clear any
data from the previous session. There's no equivalent to clear_tx_seqnum. I
suggest letting UHD do its thing and see if that's sufficient for your
needs
