Now I am able to get predictable (although not zero) phase offset with
122.88 MHz master clock. For that I have to use 12.288MHz reference
frequency so zero delay mode of lmk04816 is applied.
thanks,
Dmitry
вт, 19 июн. 2018 г. в 19:38, Ian Buckley :
> Driven from pins 14 and 15 (10MEG_R_P/N) of
Driven from pins 14 and 15 (10MEG_R_P/N) of SY89547 from page 12….that page of
FPGA pinning is redacted because it contains other proprietary info that NI
doesn’t want to release.
-Ian
> On Jun 19, 2018, at 8:20 AM, Дмитрий Михайличенко via USRP-users
> wrote:
>
> Just to clarify source of F
Just to clarify source of FPGA_REFCLK_10MHz_p/n signals (pins AG24, AH24).
I have not found them in the schematic. Do they come from SY89547 or from
LMK04816?
thanks,
Dmitry
пн, 18 июн. 2018 г. в 22:27, Ian Buckley via USRP-users <
usrp-users@lists.ettus.com>:
> Dmitry ,
> Yes that will cause yo
Dmitry ,
Yes that will cause you some pain. In this specific case the internal details
of the X310 are important.
The PPS is first sampled by a synchronizer (chain of registers) clocked with
the REF_CLK. But then there is a secondary synchronizer to the DSP clock, which
in the case of your modi
Marcus,
There is a potential ambiguity of one clock cycle (of the reference clock used
to sample the PPS) if the PPS is generated from a different clock root as the
phase of PPS w.r.t the REF_CLK slowly shifts.
This is due to the possibility of a setup/hold violation at one or both of the
sampl
OK. Now I am trying to synchronize channels on UBX only boards. I am able
to get them synchronized if I use default master clock rate 200 MHz.
For my test I use modified UHD driver that allows to set 122.88 MHz master
clock. It seems that phase sync procedure does not work in that case.
thanks,
Dm
On 06/18/2018 12:07 PM, Daniel Jepson wrote:
Dmitry,
The PPS and 10MHz should (at the very least) be generated using the
same base clock so they don't drift with respect to one another. Since
you are using multiple X310 devices, it is also important that the PPS
arrives at each device on the
Dmitry,
The PPS and 10MHz should (at the very least) be generated using the same
base clock so they don't drift with respect to one another. Since you are
using multiple X310 devices, it is also important that the PPS arrives at
each device on the exact same cycle of the 10MHz clock--otherwise you
On 06/18/2018 10:57 AM, Дмитрий Михайличенко via USRP-users wrote:
Is it important to have PPS signal aligned with reference 10 MHz
signal. In my case they come from different sources.
thanks,
Dmitry?
Something to be aware of though is that trying to achieve fine phase
synchronization (with pr
On 06/18/2018 10:57 AM, Дмитрий Михайличенко via USRP-users wrote:
Is it important to have PPS signal aligned with reference 10 MHz
signal. In my case they come from different sources.
thanks,
Dmitry?
That shouldn't matter
пн, 18 июн. 2018 г. в 17:37, Marcus D. Leech via USRP-users
mailto
Is it important to have PPS signal aligned with reference 10 MHz signal. In
my case they come from different sources.
thanks,
Dmitry?
пн, 18 июн. 2018 г. в 17:37, Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com>:
> On 06/18/2018 10:28 AM, Дмитрий Михайличенко via USRP-users wrote:
>
On 06/18/2018 10:28 AM, Дмитрий Михайличенко via USRP-users wrote:
The frequency is around 600 MHz. I also tried higher frequencies. The
offset is visible on picture attached.
thanks,
Dmitry
If you look here:
https://kb.ettus.com/UBX
You can see that for frequencies below 1GHz, you have to u
The frequency is around 600 MHz. I also tried higher frequencies. The
offset is visible on picture attached.
thanks,
Dmitry
пн, 18 июн. 2018 г. в 14:50, Дмитрий Михайличенко :
> Hi,
>
> I have a couple of X310 each of them has UBX+SBX cards. The devices are
> synchronized by external 10MHz + PPS
On 06/18/2018 07:50 AM, Дмитрий Михайличенко via USRP-users wrote:
Hi,
I have a couple of X310 each of them has UBX+SBX cards. The devices
are synchronized by external 10MHz + PPS signal. But in my test I see
random phase delay between all channels that varies between test runs.
The test crea
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