Hi Sylvain,
You are absolutely correct. We are looking at splitting the
axi_packet_gate into a buffer and a packet gate. That should effectively
reduce the address FIFO to a reasonable size and reduce the resource usage
back to reasonable levels.
Regards,
Michael
On Thu, Oct 4, 2018 at 4:10 AM
Hi Michael,
> Thank you for letting us know. That is quite a jump in utilization. We will
> take a look when we have some time.
>
> We did recently make recent bug fixes in axi_packet_gate. It looks like
> that, and possibly other changes, inadvertently increased resource
> utilization more
Hi Silvain,
Thank you for letting us know. That is quite a jump in utilization. We
will take a look when we have some time.
We did recently make recent bug fixes in axi_packet_gate. It looks like
that, and possibly other changes, inadvertently increased resource
utilization more than expected
And the culprit is axi_packet_gate
It actually uses so much more BRAMs than the MAP process replaces some
of the inferred BRAM by inferred dist ram instead to fit everything in
a B200.
Not sure why this now needs some much more resources than it did before.
Cheers,
Sylvain
Hi,
Before I spend possibly hours tracing this, I was wondering if someone
had an obvious reason for which the FPGA base design size for the B200
increases significantly between 3.9 and 3.13 ?
Just a few examples :
Number used as Memory: 4004 out of 1107236%
Number used as Mem
