Re: [USRP-users] Enable AGC in USRP E320 with RFNoC using GNURadio

at the moment. > > > > However, I cant tell you that the AGC on B2x0 devices is controlled > via > > software (using set_rx_agc()). There is no need to directly modify > the > > state of any pins of the FPGA. > > > > I vaguely remember that th

Re: [USRP-users] Enable AGC in USRP E320 with RFNoC using GNURadio

re was a bug in an earlier version of gr-uhd > (somewhere in 3.7) that made it difficult to turn on the AGC using GRC. > That particular one is fixed in gr-uhd. Not sure about gr-ettus, though. > > Maybe try using set_rx_agc() manually in you flow-graph (*.py) and see > if that helps

[USRP-users] Enable AGC in USRP E320 with RFNoC using GNURadio

Hi all, I was wondering if it is possible to enable AGC from the RFNoC radio block in GNURadio. I use UHD 4.0 version and GNURadio 3.8 with gr-ettus. I see that the RFNoC Rx radio block has an enable/disable/default AGC option in the GNURadio block which I assume calls the UHD function "set_rx_ag

Re: [USRP-users] Generate blocks with more than 1 input/output using rfnocmodtool

> > Also, as you've noticed, the generated yaml file has the wrong interface, > "fpga_iface: axis_data" should be "fpga_iface: axis_pyld_ctxt". That is a > known issue that is in the pipeline to be fixed. > > Jonathon > > On Wed, Jan 20, 2021 at 8:18 AM M

[USRP-users] Generate blocks with more than 1 input/output using rfnocmodtool

Hi all, Is it possible to automatically create an rfnoc_block schema with, for example, 2 inputs and 2 outputs payload stream packets as in the addsub blockdata using rfnocmodtool? I can generate it using rfnoc_create_verilog.py through a block.yml file following the steps in : https://kb.ettus.co

[USRP-users] Wrong name of files found when instaling OOT RFNoC block

Hi all, I have tried to install a custom OOT RFNoC block created using the rfnocmodtool. I've successfully created a module with my custom block, modifying the verilog file created by the tool ( *rfnoc-test/rfnoc/fpga/rfnoc_block_myblock/rfnoc_block_myblock.v*) to include the top level of my code

Re: [USRP-users] Fwd: FPGA RFNoC Radio block with only one channel

7;),)[INF] >> (('_device_', 'time_keeper', 'broadcaster'),)[INF] (('_device_', >> 'x300_radio', 'master'),)[INF] (('_device_', 'dram', 'slave'),)* >> >> I attach the

Re: [USRP-users] Fwd: FPGA RFNoC Radio block with only one channel

ciated DDC/DUC while leaving all the other board signals >>> connected. Again, I haven't tried it, so I can't say for sure. >>> >>> In general, these kinds of changes need to be considered carefully, >>> since it leaves signals undriven, which usually mean

[USRP-users] Fwd: FPGA RFNoC Radio block with only one channel

ware implications. > > By the way, these kinds of changes are easier to make in UHD 4.0 since > it's described by a YAML file. So it's easy to say you just want one radio > and to leave out the DDC/DUC, or DRAM FIFO, for example. The required > Verilog is then generat

[USRP-users] FPGA RFNoC Radio block with only one channel

Hi everyone, I'm using an USRP E320 using the RFNoC image to implement a code that requires too much FPGA resources. I only need to use one of the channels of the USRP so I was wondering if it could be possible to eliminate the logic associated with the other channel to save resources on the FPGA