Am I able to run make in Windows using Cygwin for ISE 14.7? I tried to run make
PROJECT_ONLY=1 , and this is what I get.
$ make PROJECT_ONLY=1
/bin/sh: xtclsh: command not found
ISE Version:
make -f Makefile.b200.inc proj NAME=B200 DEVICE=XC6SLX75 EXTRA_DEFS=" "
make[1]: Entering directory
'/cyg
B200.v is the top level Verilog file. If you inspect this file, you will
see that B200_core.v and B200_io.v are instantiated within it.
All of our FPGA code is freely available-- please take some time to look
through the files in the usrp3/lib directories here: https://github.com/
EttusResearch/f
On 04/08/2018 10:59 PM, Yeo Jin Kuang Alvin (IA) via USRP-users wrote:
Hi everyone,
I want to use the ettus code for the USRP B210, however, may I know
which is the Top file as I noticed there are 3 different ones. B200.v
, B200_core.v , B200_io.v. Tried to add the source file to Xilinx ISE
Hi everyone,
I want to use the ettus code for the USRP B210, however, may I know which is
the Top file as I noticed there are 3 different ones. B200.v , B200_core.v ,
B200_io.v. Tried to add the source file to Xilinx ISE 14.7 but there are some
files that I couldn't find, eg. Gpif_sync, slave_f
Hi,
I am allowed to do that, but how am I able to do that using ISE 14.7 together
with the USRP B210?
Thanks in advance!
From: Ian Buckley [i...@ionconcepts.com]
Sent: 07 April 2018 03:19
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject
