B200.v is the top level Verilog file. If you inspect this file, you will see that B200_core.v and B200_io.v are instantiated within it.
All of our FPGA code is freely available-- please take some time to look through the files in the usrp3/lib directories here: https://github.com/ EttusResearch/fpga/tree/maint/usrp3/lib -Robin On Mon, Apr 9, 2018 at 10:59 AM, Yeo Jin Kuang Alvin (IA) via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi everyone, > > > > I want to use the ettus code for the USRP B210, however, may I know which > is the Top file as I noticed there are 3 different ones. B200.v , > B200_core.v , B200_io.v. Tried to add the source file to Xilinx ISE 14.7 > but there are some files that I couldn’t find, eg. Gpif_sync, slave_fifo32, > uart_timing_fifo etc. > > > > What are the essentials file and where do I find it? > > > > Thanks in advance! > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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