On 04/08/2018 10:59 PM, Yeo Jin Kuang Alvin (IA) via USRP-users wrote:
Hi everyone,
I want to use the ettus code for the USRP B210, however, may I know
which is the Top file as I noticed there are 3 different ones. B200.v
, B200_core.v , B200_io.v. Tried to add the source file to Xilinx ISE
14.7 but there are some files that I couldn’t find, eg. Gpif_sync,
slave_fifo32, uart_timing_fifo etc.
What are the essentials file and where do I find it?
Thanks in advance!
There is a directory called "top":
And under that is a subdirectory callled "B200":
uhd/fpga-src/usrp3/top/b200
That is the top-level for the B200, and there's a Makefile in there that
you'll need to run:
make PROJECT_ONLY=1
which will generate a project file for the ISE GUI.
Note that Ettus don't use the ISE GUI environment for doing builds,
which is why there are makefiles that are used to produce a consistent and
reliable build process, with all the dependencies fully described,
etc. It's the only sensible way to do FPGA production builds.
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
