"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.
Signed-off-by: York Sun
---
board/freescale/common/pixis.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/common/pixis
"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.
Signed-off-by: York Sun
---
board/freescale/common/pixis.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/common/pixis.c b/board/free
for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0x together
with normal LAWs will guarantee the address is not mapped to DDR.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |4 ++--
arch/powerpc/cpu
On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.
Tested on MT36JSF2G72PZ-1G9E1 RDIMM.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c|4
arch/powerpc
CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef.
Signed-off-by: York Sun
---
include/configs/t4qds.h | 68 ---
1 file changed, 68 deletions(-)
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 1032f12
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.
Signed-off-by: York Sun
---
arch/powerpc/include/asm/config_mpc85xx.h |5 +
include/configs/B4860QDS.h|1 -
include/configs/P2041RDB.h
FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even
remote. In case none of them is defined, set it to null.
Signed-off-by: York Sun
---
drivers/net/fm/fm.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 8d70586
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun
---
arch
The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cpu.c | 23 +++
board/freescale/b4860qds/b4860qds.c | 15 ---
board/freescale/corenet_ds
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc/cpu/mpc85xx
RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for
dual rank. Single- and quad-rank are not tested due to availability.
Signed-off-by: York Sun
---
board/freescale/t4qds/ddr.h | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/board
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: York Sun
---
README
On 06/25/2013 02:24 PM, Wolfgang Denk wrote:
>
> Entry to MAINTAINERS missing. And checkpatch reports a number of
Didn't know we are enforcing this. Will add.
> warnings that need to be fixed:
>
> - WARNING: quoted string split across lines
Noticed. How are we going to balance the long lines
On 06/26/2013 03:03 PM, Wolfgang Denk wrote:
> Dear York Sun,
>
> In message <1372263479-10588-1-git-send-email-york...@freescale.com> you
> wrote:
>> Add emulator support for T4240. Emulator has limited peripherals and
>> interfaces. Difference between
On 06/27/2013 10:35 AM, Scott Wood wrote:
> On 06/27/2013 12:30:25 PM, York Sun wrote:
>> On 06/26/2013 03:03 PM, Wolfgang Denk wrote:
>> >
>> >> --- a/MAINTAINERS
>> >> +++ b/MAINTAINERS
>> >> @@ -538,6 +538,10 @@ Detlev Zundel
>>
On 06/27/2013 10:51 AM, Wolfgang Denk wrote:
> Dear York Sun,
>
> In message <51cc76b1.6030...@freescale.com> you wrote:
>>
>>> So what exactly are the changes compared to V1?
>>
>> Added entry to MAINTAINERS
>>
>> Fixed checkpatch
On Dec 25, 2013, at 10:48 PM, Prabhakar Kushwaha wrote:
> JEDEC spec requires the clocks to be stable before deasserting reset
> signal for RDIMMs. Clocks start when any chip select is enabled and
> clock control register is set. This patch also adds the interface to
> toggle memory reset signal
On 12/19/2013 07:54 PM, Nikhil Badola wrote:
> From: Ramneek Mehresh
>
> Defines get_svr() for 83xx devices
>
> Signed-off-by: Ramneek Mehresh
> ---
> arch/powerpc/cpu/mpc83xx/start.S | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/powerpc/cpu/mpc83xx/start.S
> b/arch/powe
On 12/11/2013 11:10 PM, Shengzhou Liu wrote:
> - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
> - Remove unused patameters: 'cpo', 'wrdata delay', '2T',
> which are unrelated to DDR3/3L.
>
> Signed-off-by: Shengzhou Liu
> ---
> Against master branch of git://git.denx.de/
On 12/16/2013 09:42 PM, Priyanka Jain wrote:
> Update following DDR related settings for T1040QDS
> -Correct number of chip selects to two as t1040qds supports
> two Chip selects.
> -Update board_specific_parameters udimm structure with settings
> derived via calibration.
> -Reduced I2C speed to
On 12/10/2013 11:12 PM, Prabhakar Kushwaha wrote:
> CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
> review purpose.
>
> So, use CONFIG_SPL_NAND_BOOT config.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> Changes for v2: Incorporated Scott's comments
>- Add CO
On 12/09/2013 11:43 PM, Prabhakar Kushwaha wrote:
> T1040QDS has 256KB SRAM. Comment is showing wrong information.
>
> So update the comment.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
___
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On 12/11/2013 10:39 PM, Prabhakar Kushwaha wrote:
> Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
> is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
> freqencies.
>
> So, Increase TCH as 0x8 i.e. 8 ip_clk.
>
> Signed-off-by: Prabhakar Kushwaha
>
On 12/17/2013 12:55 AM, Priyanka Jain wrote:
> Single-source clocking is new feature introduced in T1040.
> In this mode, a single differential clock is supplied to the
> DIFF_SYSCLK_P/N inputs to the processor, which in turn is
> used to supply clocks to the sysclock, ddrclock and usbclock.
>
> S
On 12/17/2013 11:21 AM, York Sun wrote:
> Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
> reduce the image size, by taking advantage of the new nand_ecclayout
> structure.
>
> Signed-off-by: York Sun
> CC: Prabhakar Kushwaha
> CC: Scott Wood
>
On 12/17/2013 11:21 AM, York Sun wrote:
> Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
> reduce the image size, by taking advantage of the new nand_ecclayout
> structure.
>
> Signed-off-by: York Sun
> CC: Prabhakar Kushwaha
> CC: Scott Wood
>
On 12/17/2013 06:27 PM, Shengzhou Liu wrote:
> CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
> update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.
>
> Signed-off-by: Shengzhou Liu
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
___
U-Boot mail
On 12/17/2013 08:11 PM, Scott Wood wrote:
> This fixes a build break due to excessively large NAND data structures.
>
> Signed-off-by: Scott Wood
> Cc: Matthias Fuchs
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
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U-B
On 12/17/2013 11:09 PM, shh@gmail.com wrote:
> From: Shaohui Xie
>
> Signed-off-by: Shaohui Xie
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
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On 12/18/2013 09:38 PM, shh@gmail.com wrote:
> From: Shaohui Xie
>
> The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1.
>
> Signed-off-by: Shaohui Xie
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
___
U-Boot mailing
On 12/25/2013 11:10 PM, Prabhakar Kushwaha wrote:
> Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start
> accessing it.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> Changes for v2: Incorporated York's comments
> - Update subject and description
>
Applied to u-boot-mpc85x
On 12/18/2013 01:50 PM, Tom Rini wrote:
> On 12/18/2013 04:35 PM, York Sun wrote:
>> On 11/25/2013 07:45 AM, Tom Rini wrote:
>>> Hello,
>>>
>>> With a recent change to U-Boot (as part of merging
>>> http://patchwork.ozlabs.org/patch/293612/), w
On 01/02/2014 09:46 PM, Shengzhou Liu wrote:
> Erratum A006379 applies to T2080/T2081 also.
>
> Signed-off-by: Shengzhou Liu
Please fix the subject. You are enabling a workaround for an erratum.
York
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Wolfgang,
I have some troubles to run MAKEALL with BUILD_NBUILDS. If I set BUILD_NBUILDS
to 2 or greater, there is a good chance the total number of targets is not an
integral multiple of BUILD_NBUILDS. It has two undesired results.
1. The status report has wrong number of passed builds.
2. This
: enable NAND boot support
powerpc/b4860/pbl: fix rcw cfg
Shengzhou Liu (1):
powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS
York Sun (2):
powerpc/P1022DS: Define new nand_ecclayout structure macros
powerpc/B4860QDS: Define new nand_ecclayout structure macros
README
On 01/06/2014 06:14 AM, Tom Rini wrote:
> On 01/02/2014 07:39 PM, Wolfgang Denk wrote:
>> Dear York,
>
>> In message <52c5fea1.7040...@freescale.com> you wrote:
>>>
>>> Are you going to remove this platform, or waiting for someone to submit a
>>> patch
>>> to do so? Does removing this platform me
On 01/06/2014 01:26 AM, Shengzhou Liu wrote:
> - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
> - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
> unrelated to DDR3/3L.
>
> Signed-off-by: Shengzhou Liu
> ---
> board/freescale/t2080qds/ddr.c | 12 ++---
Unfortunately a typo presents "DDR-A003473" instead of "DDR-A003474".
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85x
Existing workaround only handles one RDIMM on reference design. In case
two RDIMMs are used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two registers changed by the workaround.
Signed-off-by: York Sun
---
drivers/ddr/fsl/mpc85xx_ddr_gen3
On 01/08/2014 10:17 AM, York Sun wrote:
> Existing workaround only handles one RDIMM on reference design. In case
> two RDIMMs are used, the workaround requires two separate writes to
> DDR_SDRAM_MD_CNTL register.
>
> This patch also restores two registers changed by the workarou
with one and two RDIMMs
for each controller.
Signed-off-by: York Sun
Tested-by: Ben Collins
CC: James Yang
---
Change log:
v2: Revise commit message
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 59 ++--
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a
On 01/08/2014 11:24 AM, Gerhard Sittig wrote:
> On Wed, Jan 08, 2014 at 10:28 -0800, York Sun wrote:
>>
>> [ ... ]
>
> Is "474" missing at the end of the subject line?
>
No. I made a mistake to put A003474. It should be A003.
York
Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two debug registers changed by the workaround.
Signed-off-by: York Sun
CC: Ben Collins
CC: James
Troy,
I am trying to use mxc_i2c driver with multiple buses. I didn't figure out how
the bases are set. Can you shed some light on this?
Thanks,
York
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On 01/14/2014 03:25 PM, Troy Kisky wrote:
> On 1/14/2014 2:26 PM, York Sun wrote:
>> Troy,
>>
>> I am trying to use mxc_i2c driver with multiple buses. I didn't figure out
>> how
>> the bases are set. Can you shed some light on this?
>>
>> Tha
Dear Wolfgang,
On Jan 20, 2014, at 10:34 PM, Wolfgang Denk wrote:
> Dear Scott,
>
> In message <20140121054228.de994382...@gemini.denx.de> I wrote:
>>
>> I fear that more IP blocks will follow that have similar requirements,
>> and if we implemnt similar wrappers for each of them separately, we
On 01/21/2014 09:29 AM, Scott Wood wrote:
> On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote:
>> Dear York,
>>
>> In message you wrote:
>>>
On second thought, I also think we should avoid solutions where the
BE/LE test has to be done for each and every I/O accessor call again
Pantelis,
On 01/09/2014 09:52 PM, Haijun Zhang wrote:
> Card detection pin is ineffective on T4240QDS Rev1.0.
> There are two cards can be connected to board.
> 1. eMMC card is built-in board, can not be removed. so
>For eMMC card it is always there.
> 2. Card detecting pin is functional for S
On 01/10/2014 11:03 AM, Scott Wood wrote:
> On Fri, 2014-01-10 at 10:10 +0800, Po Liu wrote:
>> Using the TPL method for nand boot by sram was already
>> supported. Here add some code for mpc85xx ifc nand boot.
>>
>> - For ifc, elbc, esdhc, espi, all need the SPL without
>> section .reset
On 01/09/2014 06:10 PM, Po Liu wrote:
> Using the TPL/SPL method to booting from 8k page NAND flash.
> - Add 256kB size SRAM tlb for second step booting;
> - Add spl.c for TPL image boot;
> - Add spl_minimal.c for minimal SPL image;
> - Add C29XPCIE_NAND configure;
> -
On 01/12/2014 09:58 PM, Prabhakar Kushwaha wrote:
> Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG.
>
> Also add their details in README.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> changes for v2: Incorporated Wolfgang's comments
> - Added more description in README
>
Applied
On 01/02/2014 09:54 PM, Priyanka Jain wrote:
> Update following DDR related settings for T1040QDS
> -Correct number of chip selects to two as t1040qds supports
> two Chip selects.
> -Update board_specific_parameters udimm structure with settings
> derived via calibration.
> -Reduced I2C speed to
On 01/02/2014 10:41 PM, Nikhil Badola wrote:
> From: Ramneek Mehresh
>
> Defines get_svr() for 83xx devices
>
> Signed-off-by: Ramneek Mehresh
> ---
> Changes for v2:
> - Changed patch heading
>
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
On 01/02/2014 10:48 PM, Shengzhou Liu wrote:
> - add more serdes protocols support.
> - fix some serdes lanes route.
> - fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d.
> - correct boot location info for SD/SPI boot.
>
> Signed-off-by: Shengzhou Liu
> ---
> v2: update
On 01/05/2014 09:23 PM, Shengzhou Liu wrote:
> Enable Erratum A006379 for T2080, T2081, T4160, B4420.
>
> Signed-off-by: Shengzhou Liu
> ---
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
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On 01/12/2014 09:01 PM, Shengzhou Liu wrote:
> - Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
> - Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
> unrelated to DDR3/3L.
>
> Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s.
>
> S
On 01/13/2014 10:04 PM, Prabhakar Kushwaha wrote:
> u-boot binary size for Freescale mpc85xx platforms is 512KB.
> This has been reached to upper limit for some of the platforms causig
> linker error.
>
> So, Increase the u-boot binary size to 768KB.
>
> Signed-off-by: York
On 01/12/2014 11:32 PM, Shengzhou Liu wrote:
> This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'.
> When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before.
>
> Signed-off-by: Shengzhou Liu
> ---
Applied to u-boot-mpc85xx master branch. Awaiting upst
pc/83xx: Add support for get_svr() for 83xx devices
Shengzhou Liu (4):
powerpc/t2080qds: some update for t2080qds
powerpc/85xx: update erratum a006379
t2080qds/ddr: update ddr parameters
net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90f
York Sun (2):
powerpc/
Tom,
The following changes since commit e222b1f36fedb0363dbc21e0add7dc3848bae553:
powerpc/mpc85xx:Increase binary size for P, B & T series boards. (2014-01-21
14:06:30 -0800)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to fetch changes up to
On 01/21/2014 09:34 AM, York Sun wrote:
> On 01/21/2014 09:29 AM, Scott Wood wrote:
>> On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote:
>>> Dear York,
>>>
>>> In message you wrote:
>>>>
>>>>> On second thought, I also think
On 01/25/2014 07:46 AM, Timur Tabi wrote:
> On Fri, Jan 24, 2014 at 7:45 AM, Wolfgang Denk wrote:
>>
>> For the "test"
>> part, it is probably much easier to add a customized memory test (or
>> fix just the existing memory test such that it can be built for a 64
>> bit mode) and use this, then try
On 01/24/2014 06:19 AM, Alexander Graf wrote:
> Hrm, let me try that.
>
Looks you got plenty feedback from Scott. I am going to mark this set as "change
requested" so they will drop off from my to-do list. Please submit a v2 when
they are ready (all three patches together) with change log.
York
On 11/01/2013 12:47 AM, Zhang Haijun wrote:
> :-)
>
> Thanks.
>
> δΊ 2013/11/1 15:45, Pantelis Antoniou ει:
>> Hi Zhang,
>>
>> I'll take a look at it over the weekend.
>>
>> Regards
>>
>> -- Pantelis
>>
Where are we on this patch?
York
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On 01/20/2014 10:15 PM, Shengzhou Liu wrote:
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -973,11 +973,16 @@ Active powerpc mpc85xx-
> freescale t4qds
> Active powerpc mpc85xx- freescale t1040qds
> T1040QDS
On 01/27/2014 10:44 PM, Priyanka Jain wrote:
> This covers only non-L2 switch ethernet interfaces i.e.
> RGMII and SGMII interface for both
> -T1040RDB
> -T1042RDB_PI
>
> T1040RDB is configured as serdes protocol 0x66 which can
> support following interfaces
> -2 RGMIIS on DTSEC4, DTSEC5
> -1 SGM
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> From: Rainer Boschung
>
> -uses common deblocking algorithm from ../common/common.c
I don't see any algorithm in the common.c file.
> -supports deblocking of of I2C-bus1 by means of QRIO GPIO
> - SCL1 = GPIO_A16
> - SDA1 = GPIO_A17
>
> Q
On 01/30/2014 01:17 AM, Boschung, Rainer wrote:
> On 01/30/2014 08:32 AM, Valentin Longchamp wrote:
>> On 01/30/2014 03:30 AM, York Sun wrote:
>>> On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
>>>> From: Rainer Boschung
>>>>
>>>> -us
On 01/31/2014 04:46 AM, Valentin Longchamp wrote:
> From: Rainer Boschung
>
> This patch adds support for using some GPIOs that are connected to the
> I2C bus to force the bus lines state and perform some bus deblocking
> sequences.
>
> The KM common deblocking algorithm from board/keymile/commo
On 01/31/2014 03:16 AM, Alexander Graf wrote:
> For KVM we have a special PV machine type called "ppce500". This machine
> is inspired by the MPC8544DS board, but implements a lot less features
> than that one.
>
> It also provides more PCI slots and is supposed to be enumerated by
> device tree o
On 01/31/2014 03:16 AM, Alexander Graf wrote:
> With the qemu-ppce500 machine type we can run the same board with
> either an e500v2 or an e500mc core plugged in.
>
> This means that the IVOR setup can't be based on compile time decisions,
> so instead we have to do a runtime check which CPU gener
Tom,
The following changes since commit 07e2822d158940a0e8ba45b6ab0344ffa1011a07:
board: nios2: Check if flash is configured before calling
early_flash_cmd_reset() (2014-01-29 16:44:18 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to fet
On 01/24/2014 04:21 AM, Prabhakar Kushwaha wrote:
> T1040 has only one SerDes block. so update the code accordingly.
>
> Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85,
> 0xA7 and 0xAA
>
> Signed-off-by: Arpit Goel
> Signed-off-by: Poonam Aggrwal
> Signed-off-by: Priyanka Jain
On 01/27/2014 02:25 AM, Prabhakar Kushwaha wrote:
> Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
> - Define MDIO related configs
> - Added eth.c file
> - Update t1040.c to support RGMII and SGMII
> - Update t1040qds.c to support ethernet
> - Define the PHY addre
On 01/24/2014 11:23 PM, Prabhakar Kushwaha wrote:
> Current print only display width of PCIe device. Add print to display
> PCIe generation supported by the device.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
Applied to u-boot-mpc85xx master branch.
York
_
On 01/27/2014 12:37 AM, Priyanka Jain wrote:
> -Add usb2 node entry in "hwconfig string"
>
> -Remove controller interleaving from hwconfig string as T1040
> has only one DDR conroller
>
> -SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
> are move outside so that they are def
On 01/23/2014 12:54 PM, Poonam Aggrwal wrote:
> Removed LIODNs for RMAN, RIO, 10G. T1040 has 10 QMAN portals so assigned
> LIODNs accordingly.
>
> Signed-off-by: Poonam Aggrwal
> ---
Applied to u-boot-mpc85xx master branch.
York
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On 01/27/2014 01:11 AM, Prabhakar Kushwaha wrote:
> -Add usb2 node entry in "hwconfig string"
>
> -Remove controller interleaving from hwconfig string as T1040
> has only one DDR conroller
>
> -SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
> are move outside so that they ar
On 01/24/2014 10:41 PM, Prabhakar Kushwaha wrote:
> Due to increased size of u-boot, FMAN ucode start address has been shifted
> by 256KB causing a overlap with rootfs start address.
>
> Update rootfs start address to reflect correct memory map.
>
> Also fix minor typo in README
>
> Signed-off-b
On 01/29/2014 10:00 PM, Priyanka Jain wrote:
> This covers only non-L2 switch ethernet interfaces i.e.
> RGMII and SGMII interface for both
> -T1040RDB
> -T1042RDB_PI
>
> T1040RDB is configured as serdes protocol 0x66 which can
> support following interfaces
> -2 RGMIIS on DTSEC4, DTSEC5
> -1 SGM
On 01/27/2014 01:51 AM, Nikhil Badola wrote:
> Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual
> phy in t1040
>
> Signed-off-by: Nikhil Badola
>
Applied to u-boot-mpc85xx master branch.
York
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On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> According to the errata, some bits of an undocumented register in the
> DCSR must be set for every core in order to avoid a possible data or
> instruction corruption.
>
> This is required for the 2.0 revision of the P2041 that should be used
> as
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> From: Rainer Boschung
>
> - make use of the QRIO1 32bit register at 0x20 as bootcounter register
> - check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read
>
> Signed-off-by: Rainer Boschung
> Signed-off-by: Valentin Longchamp
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> The QRIO GPIO functions can be of general interest. They are thus added
> to a qrio.c and their prototype are available from kmp204x.h. The QRIO
> prst function are also included in this file, as well as the functions
> required for the I2C debloc
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> On the previous HW revision (now unsupported), there was a need for
> external DMA signals and thus the I2C3/4 signals were used
> DMA1_DONE/ACK/REQ.
>
> These signals now are configured as GPIO[16:19].
>
> Signed-off-by: Valentin Longchamp
> -
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> The kmcoge4 board is the product board derived from the kmlion1
> prototype. The main difference between the 2 boards is that the kmcoge4
> does not configure the Local Bus controller for LCS2.
>
> Signed-off-by: Valentin Longchamp
> ---
>
> Ch
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> The PEXHC PCIe configuration mechanism ensures that the FPGA get
> configured at power-up. Since all the PCIe devices should be configured
> when the kernel start, u-boot has to take care that the FPGA gets
> configured also in other reset scenari
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> This define can be used if the ubi boot partition (defined for all
> Keymile boards with KM_UBI_PARTITION_NAME_BOOT #define to ubi0) needs
> some additionnal boot options.
>
> This is the case for the kmp204x boards since u-boot does not support
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
> The new prototype and the final series was moved from Micron to Spansion
> to have a better reset sequence that is easier to support.
>
> Signed-off-by: Valentin Longchamp
> ---
>
> Changes in v2: None
>
Applied to u-boot-mpc85xx master branc
On 02/02/2014 11:45 PM, Valentin Longchamp wrote:
> From: Rainer Boschung
>
> This patch adds support for using some GPIOs that are connected to the
> I2C bus to force the bus lines state and perform some bus deblocking
> sequences.
>
> The KM common deblocking algorithm from board/keymile/commo
On 01/17/2014 10:58 PM, Prabhakar Kushwaha wrote:
> IFC registers can be of type Little Endian or big Endian depending upon
> Freescale SoC. Here SoC defines the register type of IFC IP.
>
> So update acessor functions with common IFC acessor functions to take care
> both type of endianness.
>
>
On 02/03/2014 01:35 PM, Scott Wood wrote:
> On Mon, 2014-02-03 at 12:28 -0800, York Sun wrote:
>> On 01/17/2014 10:58 PM, Prabhakar Kushwaha wrote:
>>> IFC registers can be of type Little Endian or big Endian depending upon
>>> Freescale SoC. Here SoC defines
On 02/04/2014 10:12 PM, Priyanka Jain wrote:
> FMAN microcode image address range on NOR flash changed from
> (0xeff0 to 0xebf1) to (0xeff1 to 0xeff1)
>
> The change has been done
> - to support FMAN microcode flashing via promjet mechanism as
> promjet uses address based on offse
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 ++-
arch/powerpc/cpu/mpc85xx/cpu_init.c |8 +---
arch/powerpc/cpu/mpc85xx/release.S|8
3 files changed, 15 insertions(+), 4
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun
---
arch/powerpc
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 -
Fix SVR checking for commit acf3f8da.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/release.S | 11 ---
1 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85xx/release.S
index 36c79d3..1860684 100644
--- a
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun
---
Change since v1:
Remove three SVRs, SVR_P1
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun
---
Change since v1
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.
Signed-off-by: York Sun
---
Change since v1:
No change.
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 ++-
arch/powerpc/cpu/mpc85xx/cpu_init.c |8 +---
arch/powerpc/cpu/mpc85xx/release.S|8
3 files
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