On 12/11/2013 10:39 PM, Prabhakar Kushwaha wrote: > Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) > is 0 i.e. 0 ns hold time on writes. This may not work on higher clock > freqencies. > > So, Increase TCH as 0x8 i.e. 8 ip_clk. > > Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com> > ---
Applied to u-boot-mpc85xx/master. Thanks. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
