On 01/02/2014 09:54 PM, Priyanka Jain wrote: > Update following DDR related settings for T1040QDS > -Correct number of chip selects to two as t1040qds supports > two Chip selects. > -Update board_specific_parameters udimm structure with settings > derived via calibration. > -Reduced I2C speed to 50KHz as DDR-SPD does not get reliably > read at 400KHz. > > Verified the updated settings to be working fine with dual-ranked > Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and > 1600MT/s. > > > Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com> > Signed-off-by: Priyanka Jain <priyanka.j...@freescale.com> > --- > Changes for v3: > Updated description based on York's comments. > > Changes for v2: > Reduced I2C speed to 50KHz. >
Applied to u-boot-mpc85xx master branch. Awaiting upstream. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
