On 01/27/2014 01:51 AM, Nikhil Badola wrote:
> Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual
> phy in t1040
>
> Signed-off-by: Nikhil Badola
>
Applied to u-boot-mpc85xx master branch.
York
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I am out for a conference. Will take a look when I get back.
York
On Nov 1, 2016 13:07, "Jagan Teki" wrote:
> On Sun, Oct 30, 2016 at 11:16 PM, Jagan Teki wrote:
> > Updated spi_flash_info table in sync with Linux, and removed
> > legacy and unsupported code.
> >
"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.
Signed-off-by: York Sun
---
board/freescale/common/pixis.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/common/pixis
"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.
Signed-off-by: York Sun
---
board/freescale/common/pixis.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/common/pixis.c b/board/free
for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0x together
with normal LAWs will guarantee the address is not mapped to DDR.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |4 ++--
arch/powerpc/cpu
On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.
Tested on MT36JSF2G72PZ-1G9E1 RDIMM.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c|4
arch/powerpc
CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef.
Signed-off-by: York Sun
---
include/configs/t4qds.h | 68 ---
1 file changed, 68 deletions(-)
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 1032f12
Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.
Signed-off-by: York Sun
---
arch/powerpc/include/asm/config_mpc85xx.h |5 +
include/configs/B4860QDS.h|1 -
include/configs/P2041RDB.h
FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even
remote. In case none of them is defined, set it to null.
Signed-off-by: York Sun
---
drivers/net/fm/fm.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 8d70586
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun
---
arch
The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cpu.c | 23 +++
board/freescale/b4860qds/b4860qds.c | 15 ---
board/freescale/corenet_ds
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc/cpu/mpc85xx
RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for
dual rank. Single- and quad-rank are not tested due to availability.
Signed-off-by: York Sun
---
board/freescale/t4qds/ddr.h | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/board
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: York Sun
---
README
lance the long lines vs split across lines?
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On 06/26/2013 03:03 PM, Wolfgang Denk wrote:
> Dear York Sun,
>
> In message <1372263479-10588-1-git-send-email-york...@freescale.com> you
> wrote:
>> Add emulator support for T4240. Emulator has limited peripherals and
>> interfaces. Difference between
On 06/27/2013 10:35 AM, Scott Wood wrote:
> On 06/27/2013 12:30:25 PM, York Sun wrote:
>> On 06/26/2013 03:03 PM, Wolfgang Denk wrote:
>> >
>> >> --- a/MAINTAINERS
>> >> +++ b/MAINTAINERS
>> >> @@ -538,6 +538,10 @@ Detlev Zundel
>>
On 06/27/2013 10:51 AM, Wolfgang Denk wrote:
> Dear York Sun,
>
> In message <51cc76b1.6030...@freescale.com> you wrote:
>>
>>> So what exactly are the changes compared to V1?
>>
>> Added entry to MAINTAINERS
>>
>> Fixed checkpatch
)
> #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
> --
> 1.7.9.5
Prabhakar,
Your patch doesn't do what the commit message says. It only enables this
feature for T1040QDS board.
York
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l get_svr
> +get_svr:
> + mfspr r3, SVR
> + blr
> +
> .globl get_pvr
> get_pvr:
> mfspr r3, PVR
>
Please share how to reproduce the compilation error. I don't see it.
York
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1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
> + {2, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
> + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
> + {2, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
> + {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b
708080A, 0x0A0B0C09, 0xff,2, 0},
> + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff,2, 0},
> + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff,2, 0},
> {}
> };
Looks you are updating timing for all speeds. Can you add to commit mess
x27;s comments
>- Add CONFIG_SPL_NAND_BOOT in README
>
Applied to u-boot-mpc85xx/master. Thanks.
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On 12/09/2013 11:43 PM, Prabhakar Kushwaha wrote:
> T1040QDS has 256KB SRAM. Comment is showing wrong information.
>
> So update the comment.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
y: Prabhakar Kushwaha
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
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's comment to move declaration to
> beginning of function.
>
> Changes for v2:
> Incorporated York's comment to separate out
> DDR_CLK_FREQ and SINGLE_SOURCE_CLK code
>
Applied to u-boot-mpc85xx/master. Thanks.
York
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On 12/17/2013 11:21 AM, York Sun wrote:
> Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
> reduce the image size, by taking advantage of the new nand_ecclayout
> structure.
>
> Signed-off-by: York Sun
> CC: Prabhakar Kushwaha
> CC: Scott Wood
>
On 12/17/2013 11:21 AM, York Sun wrote:
> Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
> reduce the image size, by taking advantage of the new nand_ecclayout
> structure.
>
> Signed-off-by: York Sun
> CC: Prabhakar Kushwaha
> CC: Scott Wood
>
On 12/17/2013 06:27 PM, Shengzhou Liu wrote:
> CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
> update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.
>
> Signed-off-by: Shengzhou Liu
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
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On 12/17/2013 08:11 PM, Scott Wood wrote:
> This fixes a build break due to excessively large NAND data structures.
>
> Signed-off-by: Scott Wood
> Cc: Matthias Fuchs
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
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On 12/17/2013 11:09 PM, shh@gmail.com wrote:
> From: Shaohui Xie
>
> Signed-off-by: Shaohui Xie
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
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On 12/18/2013 09:38 PM, shh@gmail.com wrote:
> From: Shaohui Xie
>
> The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1.
>
> Signed-off-by: Shaohui Xie
> ---
Applied to u-boot-mpc85xx/master. Thanks.
York
tion
>
Applied to u-boot-mpc85xx/master. Thanks.
York
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On 12/18/2013 01:50 PM, Tom Rini wrote:
> On 12/18/2013 04:35 PM, York Sun wrote:
>> On 11/25/2013 07:45 AM, Tom Rini wrote:
>>> Hello,
>>>
>>> With a recent change to U-Boot (as part of merging
>>> http://patchwork.ozlabs.org/patch/293612/), w
On 01/02/2014 09:46 PM, Shengzhou Liu wrote:
> Erratum A006379 applies to T2080/T2081 also.
>
> Signed-off-by: Shengzhou Liu
Please fix the subject. You are enabling a workaround for an erratum.
York
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script throws out SIGTERM.
The second one is troubling me. I am using Jenkins to monitor and build
automatically. I can trap the SIGTERM on some hosts but not all of them.
Can you shed some light on this?
York
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: enable NAND boot support
powerpc/b4860/pbl: fix rcw cfg
Shengzhou Liu (1):
powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS
York Sun (2):
powerpc/P1022DS: Define new nand_ecclayout structure macros
powerpc/B4860QDS: Define new nand_ecclayout structure macros
README
On 01/06/2014 06:14 AM, Tom Rini wrote:
> On 01/02/2014 07:39 PM, Wolfgang Denk wrote:
>> Dear York,
>
>> In message <52c5fea1.7040...@freescale.com> you wrote:
>>>
>>> Are you going to remove this platform, or waiting for someone to submit a
>>&
h. Second, please add change log.
Please add information about tested conditions, including DIMM model and speed.
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Unfortunately a typo presents "DDR-A003473" instead of "DDR-A003474".
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85x
Existing workaround only handles one RDIMM on reference design. In case
two RDIMMs are used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two registers changed by the workaround.
Signed-off-by: York Sun
---
drivers/ddr/fsl/mpc85xx_ddr_gen3
On 01/08/2014 10:17 AM, York Sun wrote:
> Existing workaround only handles one RDIMM on reference design. In case
> two RDIMMs are used, the workaround requires two separate writes to
> DDR_SDRAM_MD_CNTL register.
>
> This patch also restores two registers changed by the workarou
with one and two RDIMMs
for each controller.
Signed-off-by: York Sun
Tested-by: Ben Collins
CC: James Yang
---
Change log:
v2: Revise commit message
drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 59 ++--
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a
On 01/08/2014 11:24 AM, Gerhard Sittig wrote:
> On Wed, Jan 08, 2014 at 10:28 -0800, York Sun wrote:
>>
>> [ ... ]
>
> Is "474" missing at the end of the subject line?
>
No. I made a mistake to put A003474. It should be A003.
York
Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.
This patch also restores two debug registers changed by the workaround.
Signed-off-by: York Sun
CC: Ben Collins
CC: James
Troy,
I am trying to use mxc_i2c driver with multiple buses. I didn't figure out how
the bases are set. Can you shed some light on this?
Thanks,
York
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On 01/14/2014 03:25 PM, Troy Kisky wrote:
> On 1/14/2014 2:26 PM, York Sun wrote:
>> Troy,
>>
>> I am trying to use mxc_i2c driver with multiple buses. I didn't figure out
>> how
>> the bases are set. Can you shed some light on this?
>>
>> Tha
once, and for example set
> function pointers as needed (hoping that this driver will only be
> needed after relocation, so we have writable data segment).
I like the idea of setting it just once, but I don't see how to implement it. A
poi
On 01/21/2014 09:29 AM, Scott Wood wrote:
> On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote:
>> Dear York,
>>
>> In message you wrote:
>>>
>>>> On second thought, I also think we should avoid solutions where the
>>>> BE/LE test has
instead of code in driver
> changes for V2:
> - Add the judgement condition for this broken card
>
I think this set of patches are in your backyard. If you ack them, I can apply
them to mpc85xx.
http://patchwork.ozlabs.org/patch/309168/
http://patchwork.ozlabs.org/patch/309167/
gt;> drivers/mtd/nand/fsl_ifc_spl.c | 31 ---
>> spl/Makefile | 1 +
>> 4 files changed, 34 insertions(+), 14 deletions(-)
>
> Acked-by: Scott Wood
>
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
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move the 8k TLB from 0xe000 to 0x
> - change the ddr tlb mapping condition
> changes for v4:
> - None.
> changes for v5:
> - code style change.
> changes for v6:
> - none
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
iption in README
>
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
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igned-off-by: Priyanka Jain
> ---
> Changes for v3:
> Updated description based on York's comments.
>
> Changes for v2:
> Reduced I2C speed to 50KHz.
>
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
__
On 01/02/2014 10:41 PM, Nikhil Badola wrote:
> From: Ramneek Mehresh
>
> Defines get_svr() for 83xx devices
>
> Signed-off-by: Ramneek Mehresh
> ---
> Changes for v2:
> - Changed patch heading
>
Applied to u-boot-mpc85xx master branc
Liu
> ---
> v2: update to support more serdes, applied in Gerrit sdk.
>
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
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On 01/05/2014 09:23 PM, Shengzhou Liu wrote:
> Enable Erratum A006379 for T2080, T2081, T4160, B4420.
>
> Signed-off-by: Shengzhou Liu
> ---
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
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Z-2G1K1 and verified speed 1200/1866/2133MT/s.
>
> Signed-off-by: Shengzhou Liu
> ---
> v3: fix issue of two line with same parameters and add more commit
> description.
> v2: rebase.
Applied to u-boot-mpc85xx master branch. Awaiting upstream.
York
__
On 01/13/2014 10:04 PM, Prabhakar Kushwaha wrote:
> u-boot binary size for Freescale mpc85xx platforms is 512KB.
> This has been reached to upper limit for some of the platforms causig
> linker error.
>
> So, Increase the u-boot binary size to 768KB.
>
> Signed-off-by: York
x master branch. Awaiting upstream.
York
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pc/83xx: Add support for get_svr() for 83xx devices
Shengzhou Liu (4):
powerpc/t2080qds: some update for t2080qds
powerpc/85xx: update erratum a006379
t2080qds/ddr: update ddr parameters
net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90f
York Sun (2):
powerpc/
|9 +
include/configs/T4240QDS.h|8
4 files changed, 49 insertions(+)
Thanks,
York
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On 01/21/2014 09:34 AM, York Sun wrote:
> On 01/21/2014 09:29 AM, Scott Wood wrote:
>> On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote:
>>> Dear York,
>>>
>>> In message you wrote:
>>>>
>>>>> On second thought, I also think
. It will remap back the window, as you
would see the message on the console.
York
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On 01/24/2014 06:19 AM, Alexander Graf wrote:
> Hrm, let me try that.
>
Looks you got plenty feedback from Scott. I am going to mark this set as "change
requested" so they will drop off from my to-do list. Please submit a v2 when
they are ready (all three patches together) with c
On 11/01/2013 12:47 AM, Zhang Haijun wrote:
> :-)
>
> Thanks.
>
> δΊ 2013/11/1 15:45, Pantelis Antoniou ει:
>> Hi Zhang,
>>
>> I'll take a look at it over the weekend.
>>
>> Regards
>>
>> -- Pantelis
>>
Where are we on this
RD,DEVELOP
> Dirk Eibach
>
> Active powerpc mpc85xx- gdsys p1022
> controlcenterd_TRAILBLAZER
> controlcenterd:TRAILBLAZER,SPIFLASH
R);
> +#endif
> + case PHY_INTERFACE_MODE_RGMII:
> + if (FM1_DTSEC4 == i)
> + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
> + if (FM1_DTSEC5 == i)
> + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
> + fm_info_set_phy_address(i, phy_addr);
Compiling warning here
warning: 'phy_addr' may be used uninitialized in this function
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configured as output that drives low
> + * -> 1 GPIO configured as input pull-up ties high
> + */
> +
I failed to understand these comments as well. Are these comments copy-n-paste?
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On 01/30/2014 01:17 AM, Boschung, Rainer wrote:
> On 01/30/2014 08:32 AM, Valentin Longchamp wrote:
>> On 01/30/2014 03:30 AM, York Sun wrote:
>>> On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
>>>> From: Rainer Boschung
>>>>
>>>> -us
ing GPIOs input, but 0 value for open drain */
> + qrio_gpio_direction_input(DBLK_PORT1, DBLK_SCL1);
> + qrio_gpio_direction_input(DBLK_PORT1, DBLK_SDA1);
> +
> + qrio_set_gpio(DBLK_PORT1, DBLK_SCL1, 0);
> + qrio_set_gpio(DBLK_PORT1, DBLK_SDA1, 0);
> +}
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CONFIG_SYS_DDR_SDRAM_BASE
> +
> +#define CONFIG_CHIP_SELECTS_PER_CTRL 0
I don't know if the qemu has PCI, DDR, etc. Setting the above line to 0 will
actually disable DDR controllers. Is that what you want?
> +
> +/* Get RAM size from device tree */
> +#define CONFIG_DDR_SPD
You enabled SPD but I don't see the I2C address. Did you miss something, or you
don't really use SPD?
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erformance monitor */
>
> -/* e500mc only */
> -#ifdef CONFIG_E500MC
> + /* e500mc only */
> + blt 2f
This "blt" has a risk. Please put a comment warning developers who will modify
the code to be sure the flag has not been updated since last "cmpw".
York
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+-
include/fsl_ifc.h | 42 +-
34 files changed, 1230 insertions(+), 361 deletions(-)
create mode 100644 board/freescale/t1040qds/eth.c
create mode 100644 board/freescale/t104xrdb/eth.c
create mode 100644 board/keymile/kmp204x/qrio.c
Thanks,
York
Signed-off-by: Priyanka Jain
> Signed-off-by: Prabhakar Kushwaha
> ---
Applied to u-boot-mpc85xx master branch.
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- Define the PHY address
>
> Signed-off-by: Arpit Goel
> Signed-off-by: Bhupesh Sharma
> Signed-off-by: Poonam Aggrwal
> Signed-off-by: Priyanka Jain
> Signed-off-by: Prabhakar Kushwaha
>
> ---
> Changes for v2:
> - Added missed sign off
&g
On 01/24/2014 11:23 PM, Prabhakar Kushwaha wrote:
> Current print only display width of PCIe device. Add print to display
> PCIe generation supported by the device.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
Applied to u-boot-mpc85xx maste
correct usb1 string for ;
>
Applied to u-boot-mpc85xx master branch.
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On 01/23/2014 12:54 PM, Poonam Aggrwal wrote:
> Removed LIODNs for RMAN, RIO, 10G. T1040 has 10 QMAN portals so assigned
> LIODNs accordingly.
>
> Signed-off-by: Poonam Aggrwal
> ---
Applied to u-boot-mpc85xx master branch.
York
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are move outside so that they are defined for all cases as these
> macros are also used by other u-boot code
>
> -Add CONFIG_SYS_CSPR2_EXT to make cpld accessible in u-boot
>
> Signed-off-by: Prabhakar Kushwaha
>
> ---
> Changes for v2:
> correct usb1 st
ME
>
> Signed-off-by: Prabhakar Kushwaha
> ---
Applied to u-boot-mpc85xx master branch.
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v2:
> Initialized phy_addr to remove compilation warning.
>
>
Applied to u-boot-mpc85xx master branch.
York
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On 01/27/2014 01:51 AM, Nikhil Badola wrote:
> Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual
> phy in t1040
>
> Signed-off-by: Nikhil Badola
>
Applied to u-boot-mpc85xx master branch.
York
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should be used
> as soon as available in our design.
>
> Signed-off-by: Valentin Longchamp
> ---
>
> Changes in v2: None
Applied to u-boot-mpc85xx master branch.
York
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gned-off-by: Valentin Longchamp
>
> ---
>
> Changes in v2:
> - change bootcounter implementation to use generic driver
>
Applied to u-boot-mpc85xx master branch.
York
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for the I2C deblocking support (open-drain).
>
> Signed-off-by: Valentin Longchamp
> ---
>
> Changes in v2: None
>
Applied to u-boot-mpc85xx master branch.
York
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y: Valentin Longchamp
> ---
>
> Changes in v2: None
>
Applied to u-boot-mpc85xx master branch.
York
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entin Longchamp
> ---
>
> Changes in v2: None
>
Applied to u-boot-mpc85xx master branch.
York
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v2: None
>
Applied to u-boot-mpc85xx master branch.
York
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ntin Longchamp
> ---
>
> Changes in v2: None
>
Applied to u-boot-mpc85xx master branch.
York
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to u-boot-mpc85xx master branch.
York
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rite the commit message and and the comments for more clarity
> - fix the GPIO numbers that where not correct
>
> Changes in v2: None
>
Applied to u-boot-mpc85xx master branch.
York
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e of endianness.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
> Changes for v2:
> - fix spelling mistakes
>
Applied to u-boot-mpc85xx master branch.
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On 02/03/2014 01:35 PM, Scott Wood wrote:
> On Mon, 2014-02-03 at 12:28 -0800, York Sun wrote:
>> On 01/17/2014 10:58 PM, Prabhakar Kushwaha wrote:
>>> IFC registers can be of type Little Endian or big Endian depending upon
>>> Freescale SoC. Here SoC defines
t flash is 0x1
>
> - FMAN microcode is of size 64KB so it will fit into
> 0xeff1 to 0xeff1.
>
NACK.
The tool is not broken. I have made a configuration to use PROMJET to download
all images successfully.
York
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Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 ++-
arch/powerpc/cpu/mpc85xx/cpu_init.c |8 +---
arch/powerpc/cpu/mpc85xx/release.S|8
3 files changed, 15 insertions(+), 4
Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.
Signed-off-by: York Sun
---
arch/powerpc
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 -
Fix SVR checking for commit acf3f8da.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/release.S | 11 ---
1 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85xx/release.S
index 36c79d3..1860684 100644
--- a
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun
---
Change since v1:
Remove three SVRs, SVR_P1
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