MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK
defconfig, then cause SPL boot failure.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +-
arch/arm/dts/imx8mm-evk.dtsi| 127 +++-
2 files changed, 68 insertions(+), 63 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
b/arch/arm
Hi Paul,
On 6/24/2024 8:09 PM, Fabio Estevam wrote:
Hi Paul,
On Fri, Jun 21, 2024 at 10:06 AM Paul Geurts
wrote:
-struct imx_sec_config_fuse_t {
+struct imx_fuse_t {
Please make the struct renaming a separate patch.
Peng Fan, Ye Li,
Could you please help review this patch?
Thanks
separate patch.
Peng Fan, Ye Li,
Could you please help review this patch?
Thanks
Can you take a look iMX8MP FIELD_RETURN fuse, I think it does not have 1 bit
but 8 bits which requires to burn a sequence. Only when the bits sequence is
matched, the field return can work. So checking the bit 0 is
{
+struct imx_fuse_t {
Please make the struct renaming a separate patch.
Peng Fan, Ye Li,
Could you please help review this patch?
Thanks
Can you take a look iMX8MP FIELD_RETURN fuse, I think it does not
have 1 bit but 8 bits which requires to burn a sequence. Only when
the bits sequence is
I think there is no particular SW support needed for FIELD_RETURN on 8MN.
From what you described, you have moved the part from closed to FIELD_RETURN.
So are you
able to boot into SPL without signature?
Best regards,
Ye Li
> -Original Message-
> From: Peng Fan (OSS)
> Sent:
Hi Thomas,
It is due to ARMV8_SPL_EXCEPTION_VECTORS not enabled by default in
upstream. I will send a patch
Best regards,
Ye Li
> -Original Message-
> From: Thomas Schaefer
> Sent: Thursday, January 11, 2024 9:40 PM
> To: Ye Li ; Peng Fan (OSS) ;
> 'u-boot@
To work with commit 2f3c920(imx8m: workaround ROM serror),
we need to enable the SError exception and install vector in SPL.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8m/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/mu.h
b/arch
This event callback imx9_probe_mu needs to be called in board_r
as well, because many ELE APIs depending on this MU probed
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx9/soc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index
The size for flexspi AHB buffer space is wrong, so correct it.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/imx9/soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 15e87b8..2117489 100644
--- a/arch/arm/mach
imx_tmu_arch_init does not implement for iMX8MQ, error is returned
Signed-off-by: Ye Li
---
drivers/thermal/imx_tmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index 4721cfb..ca775e5 100644
--- a/drivers/thermal/imx_tmu.c
+++ b
The spl_spi_get_uboot_offs weak function is defined unsigned int.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/image-container.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/image-container.c
b/arch/arm/mach-imx/image-container.c
index c9455fe..35da0ae
Change to regulator_set_enable_if_allowed to avoid enable failure,
in case same phy supply shared by multiple FEC controllers.
Signed-off-by: Ye Li
---
drivers/net/fec_mxc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
Changes in v2:
Fix imx93_var_som and phycore_imx93 as well
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
board/phytec/phycore_imx93/spl.c| 2
Since the event callback imx9_probe_mu is re-defined, update
its prototype.
Signed-off-by: Ye Li
---
Changes in v2:
Fix imx93_var_som and phycore_imx93 as well
arch/arm/include/asm/arch-imx9/mu.h | 2 +-
board/freescale/imx93_evk/spl.c | 2 +-
board/phytec/phycore_imx93/spl.c| 2
This event callback imx9_probe_mu needs to be called in board_r
as well, because many ELE APIs depending on this MU probed
Signed-off-by: Ye Li
---
No changes in v2
arch/arm/mach-imx/imx9/soc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx
The patch in commit cf8dcc5d02c32173b74bf1b7600dd2b990a90b13 is not correct,
it will append fdt to each loadable image.
Actually when using TINY FIT, the first loadable image is thought as u-boot
and already have fdt appended.
Signed-off-by: Ye Li
---
common/spl/spl_fit.c | 4
1 file
Commit cf8dcc5d02c3 ("common: spl_fit: Default to IH_OS_U_BOOT if
FIT_IMAGE_TINY enabled") is not correct, it will append fdt to each loadable
image. Actually when using TINY FIT, the first loadable image is thought as
u-boot and already have fdt appended.
Signed-off-by: Ye Li
Tested
Hi Michael,
> -Original Message-
> From: Michael Nazzareno Trimarchi
> Sent: Thursday, July 15, 2021 2:52 PM
> To: Peng Fan (OSS)
> Cc: Peng Fan ; U-Boot-Denx ;
> Stefano Babic ; Ye Li ; Fabio Estevam
> ; Jagan Teki
> Subject: [EXT] Re: Problem on imx: add r
Hi Stefano,
Ok. I will rebase the patches after the 8ULP is merged.
Best regards,
Ye Li
> -Original Message-
> From: Stefano Babic
> Sent: Saturday, July 17, 2021 8:54 PM
> To: Ye Li ; sba...@denx.de; u-boot@lists.denx.de; Peng Fan
> ; ma...@denx.de
> Cc: rfried
Add phy-reset-duration and phy-reset-post-delay to FEC node for PHY
reset, otherwise the PHY does not work correctly.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
b/arch/arm/dts/imx8mp-evk
Parse the "phy-reset-gpios", "phy-reset-post-delay" and
"phy-reset-duration" properties from eqos node to control the
ethernet PHY reset at driver probe.
Reset PHY once is enough that can reduce the time cost to
get IP after the first time.
Signed-off-by: Ye Li
i.MX8MP has two ENET controllers, have to update the function to
enable loading two MAC addresses.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/mac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
index 3b1496b..9bb63d2 100644
i.MX8MP has one DWC EQoS controller, so allow to build mac.c when
only this driver is enabled.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 1aa26a5..df2253d 100644
--- a/arch
Add node for EQoS ethernet controller as the second ethernet port
on i.MX8MP
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index ecccfbb..813dc66 100644
--- a
i.MX8MP EVK has two ethernet ports. Add relevant nodes and properties
for EQoS port to the EVK DTS file.
In -u-boot.dtsi, change the u-boot eqos compatible string, add PHY
reset gpio and remove assigned clocks as not supported in CCF.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi
The setup functions should be independent for two ethernet controllers
Signed-off-by: Ye Li
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
Since we uses the DTS and PHY reset gpio in EQoS driver to do the
reset, remove the duplicated codes from board file.
Signed-off-by: Ye Li
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
DWC EQOS driver has removed to use noncached memory, so delete
the configuration from iMX8MP EVK head file.
Signed-off-by: Ye Li
---
include/configs/imx8mp_evk.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 4850b1b
Enable the EQoS i.MX driver in defconfig, also enable the PHYLIB
to facilitate the case that only has FEC enabled.
Signed-off-by: Ye Li
---
configs/imx8mp_evk_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index
the DTOCV to 0xE, the max setting, this also align
with Linux configuration.
Signed-off-by: Haibo Chen
Reviewed-by: Ye Li
---
drivers/mmc/fsl_esdhc_imx.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index e0e1326..7b31ed8
2021 - 16:43:04 -0800)
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
Signed-off-by: Ye Li
---
configs/mx6sabreauto_defconfig | 1 +
configs/mx6sabresd_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs
XN bit, and set domain to client
to enable the XN and access check. So speculative instruction fetch can only
happens on these 3 regions to avoid prefetch from peripherals and invalid
regions.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/cache.c | 49
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-imx8mq-usb.c | 197 +++
3 files changed, 205 insertions(+)
create
Add alias for two DWC3 usb controllers to fix the seq index.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mq.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index a841a02..a44f729 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm
Add clock function to setup relevant clocks for USB3.0 controllers and
PHYs on i.MX8MQ
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx8m/clock.h | 1 +
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 22 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/include
Setup USB clock in board codes, and enable the DWC3 XHCI and
PHY drivers to make USB3.0 host port working on i.MX8MQ EVK.
Signed-off-by: Ye Li
---
board/freescale/imx8mq_evk/imx8mq_evk.c | 4
configs/imx8mq_evk_defconfig| 9 +
2 files changed, 13 insertions(+)
diff
Hi Fabio,
On Thu, 2021-02-25 at 08:01 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> Hi Ye Li,
>
> On Thu, Feb 25, 2021 at 3:36 AM Ye Li wrote:
> >
> >
> > Setup USB clock in board codes, and enable the DWC3 XHCI and
> > PHY drivers to make
/* TCM */
> .virt = 0x7CUL,
> --
> 2.30.0
>
OCRAM_S is used by ATF and SPL to pass DDR CSR data. It is better not
use it in u-boot to avoid any DDR issue.
And this imx8m_mem_map will be modified at runtime to get rid of optee
memory. When OCRAM_S is added, the index used in enable_caches and
dram_init need update as well.
Best regards,
Ye Li
ALIGN_IMX(sbuf.st_size + sizeof(imx_header_v3_t) +
> ivt_offset,
> sector_size);
>
> image_off = header_image_off + sizeof(imx_header_v3_t);
> --
> 2.25.1
>
Tested-by: Ye Li
Best regards,
Ye Li
Hi Fabio,
On Thu, 2021-02-25 at 10:49 -0300, Fabio Estevam wrote:
> Caution: EXT Email
>
> Hi Ye Li,
>
> On Thu, Feb 25, 2021 at 10:34 AM Ye Li wrote:
>
> >
> > Sure, I have tested it on 8mq evk. I can reproduce the two issues
> > you
> > met.
>
Hi Marek,
On Fri, 2021-02-26 at 13:44 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 2/26/21 8:15 AM, Ye Li wrote:
> >
> > Hi Marek,
> >
> > On Thu, 2021-02-25 at 21:52 +0100, Marek Vasut wrote:
> > >
> > > Caution: EXT Email
> &
CT tests on USB disk. The
USB_ASYNCLISTADDR register is changed to a invalid address when the
issue happens. It is fixed after adding the IAA handshake.
Signed-off-by: Ye Li
---
drivers/usb/host/ehci-hcd.c | 25 +
drivers/usb/host/ehci.h | 1 +
2 files changed, 26 inse
Hi Marek,
On Mon, 2021-03-08 at 09:50 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/8/21 4:35 AM, Ye Li wrote:
> [...]
> >
> > +static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
> > +{
> > + u32 cmd, status;
> > + int ret;
> >
Hi Marek,
On Tue, 2021-03-09 at 09:08 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/9/21 4:18 AM, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> [...]
>
> >
> > >
> > > >
> > > >
> > >
meout errors like
EHCI timed out on TD - token=0x801f8c80
Signed-off-by: Ye Li
---
Changes in v2:
- Remove unnecessary cast and parenthesis
- Abort the transfer when IAA cycle timeout
- Add steps to reproduce the issue
drivers/usb/host/ehci-hcd.c | 27 +++
drivers
On Mon, 2020-06-29 at 12:11 +0200, Sébastien Szymanski wrote:
> Caution: EXT Email
>
> On 6/29/20 11:51 AM, Ye Li wrote:
> >
> > On Mon, 2020-06-29 at 10:42 +0200, Sébastien Szymanski wrote:
> > >
> > > Caution: EXT Email
> > >
> > >
On Tue, 2020-06-30 at 15:03 +0200, Sébastien Szymanski wrote:
> Caution: EXT Email
>
> Quoting Ye Li from NXP:
>
> "We have confirmed with PMIC team, 0x35 is used only on early
> chips
> and not used any more. 0x25 is the final address."
>
> Fix
Hi Matt,
> -Original Message-
> From: Matt Porter
> Sent: 2020年4月8日 5:38
> To: Ye Li
> Cc: tr...@konsulko.com; u-boot@lists.denx.de; Fabio Estevam
> ; Peng Fan ; Abel Vesa
> ; dl-uboot-imx
> Subject: [EXT] Re: [PATCH] Revert "common: spl_fit: Default to
>
correct script by moving u-boot to firmware and ATF to loadable.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/mkimage_fit_atf.sh | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh
b/arch/arm/mach-imx/mkimage_fit_atf.sh
index ad81d5e
t expects to be
burn at 32KB offset.
The fit offset 0x6 has already included the 32KB offset. So when you burn
this flash.bin
to emmc boot partition at offset 0, the fit offset should subtract the 32KB
(0x6 - 0x8000).
Best regards,
Ye Li
>
> Best regards,
> Stefano Babic
selecting cs.
Signed-off-by: Ye Li
Reviewed-by: Ashish Kumar
Reviewed-by: Kuldeep Singh
---
drivers/spi/fsl_qspi.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e715f98..d9f531a 100644
--- a
)
to address above problem.
When the config is set:
1. Full AHB space is divided to each CS.
2. A dedicated LUT entry is used for AHB read only.
3. The MODE instruction in LUT is replaced to standard ADDR instruction
4. The address in spi_mem_op is used to SFAR and AHB read
Signed-off-by: Ye Li
-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/mach-imx/imx8/image.c | 81 +++---
1 file changed, 76 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/imx8/image.c b/arch/arm/mach-imx/imx8/image.c
index 5abc0d3..bd0e0a2 100644
--- a/arch/arm/mach
Add SCFW API sc_misc_get_boot_container to get current boot container
set index.
The index value returns 1 for primary container set, 2 for secondary
container set.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/sci/rpc.h | 1 +
arch/arm/include/asm/arch-imx8
index in PARTITION_CONFIG register, but have
to check the secondary boot for using correct boot partition.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
common/spl/spl_mmc.c | 35 ++-
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/common/spl/spl_mm
Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX
platforms, so we have to adjust the index accordingly.
Signed-off-by: Adrian Alonso
Signed-off-by: Ye Li
---
drivers/gpio/mxc_gpio.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/mxc_gpio.c
c70, seq 1, (req 0)
2 * gpio@5d0a @ fbaefd50, seq 2, (req 1)
3 * gpio@5d0b @ fbaefe30, seq 5, (req 2)
4 * gpio@5d0c @ fbaeff10, seq 3, (req 3)
5 * gpio@5d0d @ fbaefff0, seq 4, (req 4)
6 * gpio@5d0e @ fbaf00d0, seq 6, (req 5)
7 * gpio@5d0f @ fbaf01b0, seq 7, (r
by using
ofdata_to_platdata and using DM framework to allocate platdata.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
drivers/gpio/mxc_gpio.c | 36 +---
1 file changed, 9 insertions(+), 27 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio
(req -1)
1 clk @ fce23110
uclass 67: pinctrl
0 * iomuxc @ fce22470, seq 0, (req -1)
1 iomuxc @ fce231c0
After the fix:
uclass 24: clk
0 * clk @ fce22380, seq 0, (req -1)
uclass 67: pinctrl
0 * iomuxc @ fce22470, seq 0, (req -1)
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
drivers
.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
drivers/i2c/imx_lpi2c.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index c8e42e0..b7b2aaf 100644
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c
Fix the bug that multiple lines wraps to overwrite logo bmp
display.
Signed-off-by: Ye Li
---
drivers/video/vidconsole-uclass.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/video/vidconsole-uclass.c
b/drivers/video/vidconsole-uclass.c
index d30e6db..9b76154 100644
--- a/drivers
Update video bmp codes to support 8 bits BMP to 32 bits conversion
so that we can display 8 bits logo on 24 bits or 32 bits display
Signed-off-by: Ye Li
---
drivers/video/video_bmp.c | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers
,
Signed-off-by: Ye Li
---
common/splash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/splash.c b/common/splash.c
index e7d8477..2b9313e 100644
--- a/common/splash.c
+++ b/common/splash.c
@@ -59,7 +59,7 @@ static struct splash_location default_splash_locations
SIZE
> hex "Maximum size for Command Sequence File (CSF) binary"
> + default 0x2000 if IMX_HAB
I suggest using "default 0x2000 if ARCH_IMX8M", because i.MX6/7 may also enable
IMX_HAB.
Best regards,
Ye Li
> default 0x2060
>
Hi Tom,
> -Original Message-
> From: Tom Rini
> Sent: 2020年6月11日 20:12
> To: Ye Li
> Cc: u-boot@lists.denx.de; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx
> Subject: Re: [EXT] [PATCH 24/30] arm: imx: Finish migration of
> CONFIG_CSF_SIZE to Kconfig
>
>
T
> > symbol. Update things so that CSF_SIZE itself depends on IMX_HAB
> > being
> > enabled and provide the default value for i.MX8M family of parts.
> >
> > Cc: Stefano Babic
> > Cc: Fabio Estevam
> > Cc: Ye Li
> > Cc: NXP i.MX U-Boot Tea
p->name = pca9450_name;
> p->interface = PMIC_I2C;
> p->number_of_regs = PCA9450_REG_NUM;
> - p->hw.i2c.addr = 0x35;
> + p->hw.i2c.addr = 0x25;
The address 0x35 is correct for PCA9540A. You are probably using
PCA9540B/C which address is 0x2
Hi Marek,
On Wed, 2022-03-23 at 22:16 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/23/22 03:42, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> >
> > >
> > > >
> > > > >
> > > > > diff --git a/arch/arm
controller. So once
removed usb_hub, the power domain is power off before removing USB controller.
Signed-off-by: Ye Li
---
common/usb_hub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/usb_hub.c b/common/usb_hub.c
index ba11a18..990993a 100644
--- a/common/usb_hub.c
andle the page unaligned offset,
but the spl_simple_fit_read can't do it. spl_simple_fit_read requires
the FIT location at page aligned offset.
Hence, remove the nand_get_mtd overwrite function from mxs_nand_spl
to use page unaligned read by driver.
Signed-off-by: Ye Li
---
drivers/mt
On Mon, 2022-03-28 at 16:54 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/28/22 08:54, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> [...]
>
> >
> > >
> > > >
> > > > 2. Update the u-boot.itb offset in imx8mp-u-bo
Because mxs_nand_spl driver does not support DM, to use the minimum ECC
layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC.
Signed-off-by: Ye Li
---
drivers/mtd/nand/raw/mxs_nand.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd
On Tue, 2022-03-29 at 11:01 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/29/22 04:49, Ye Li wrote:
>
> Hi,
>
> >
> > >
> > > >
> > > > If you change the ROM API driver, that will break our design.
> > > > You
&g
On Thu, 2022-03-31 at 00:27 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/29/22 11:56, Ye Li wrote:
>
> Hi,
>
> >
> > >
> > > >
> > > > But once you want to upgrade the
> > > > flash.bin, flexspi configurations wi
Because mxs_nand_spl driver does not support DM, to use the minimum ECC
layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC.
Signed-off-by: Ye Li
Reviewed-by: Han Xu
---
Changes in v2:
- Use IS_ENABLED to replace #ifdef
drivers/mtd/nand/raw/mxs_nand.c | 3 +++
1 file changed, 3
pll2_200m", "sys_pll1_40m",
> "sys_pll2_100m",
> "sys_pll1_800m",
> "sys_pll2_500m", "clk_ext4",
> "audio_pll2_out" };
> @@ -324,6 +336,8
Get and print boot stage through ROM API in SPL
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 7 +++
arch/arm/mach-imx/spl_imx_romapi.c| 22 +-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/arm
PCA9451A uses similar BUCKs and LDO regulators as PCA9450B/C but
has LDO2 and LDO3 removed. So reuse pca9450 PMIC and regulator driver
and add new type for PCA9451A.
Signed-off-by: Ye Li
---
drivers/power/pmic/pca9450.c | 1 +
drivers/power/regulator/pca9450.c | 11 ++-
include
Mn0%3D%7C1000&sda
> ta=Fo5efFghnqsyUvtuykwVm68NvDnk%2Fb1hCoiuQW1JkiA%3D&reserved=0
>
> ?
>
The fit buffer was used in SPL is a fit size related offset to u-boot
base. In mkimage, we generate IVT following the same calculation. So we
don't use ivt-&
t; release.
> > > > Thanks for explaining, I'll pick up the revert patch then.
> > > >
> > > > For your LMB tree, I like the initial approach but looking at
> > > > 528915c71762 ("imx: Fix potential lmb memory overwritten by
> >
return (void *)((CONFIG_SYS_TEXT_BASE -
> CONFIG_FIT_EXTERNAL_OFFSET));
It looks odd to use CONFIG_FIT_EXTERNAL_OFFSET. This config is used
to designate the image offset inside the FIT. It is irrelevant here.
Please follow the patch 719d665a87c6: ("MLK-20467 imx8m: Fix issue for
booting
i.MX8MP has two ENET controllers, have to update the function to
enable loading two MAC addresses.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/mac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c
index 3b1496b..9bb63d2 100644
i.MX8MP EVK has two ethernet ports. Add relevant nodes and properties
for EQoS port to the EVK DTS file.
In -u-boot.dtsi, change the u-boot eqos compatible string, add PHY
reset gpio and remove assigned clocks as not supported in CCF.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi
i.MX8MP has one DWC EQoS controller, so allow to build mac.c when
only this driver is enabled.
Signed-off-by: Ye Li
---
arch/arm/mach-imx/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0ef2695..74a2a2a 100644
--- a/arch
The setup functions should be independent for two ethernet controllers
Signed-off-by: Ye Li
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
b/board/freescale/imx8mp_evk/imx8mp_evk.c
Since we uses the DTS and PHY reset gpio in EQoS driver to do the
reset, remove the duplicated codes from board file.
Signed-off-by: Ye Li
---
board/freescale/imx8mp_evk/imx8mp_evk.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
DWC EQOS driver has removed to use noncached memory, so delete
the configuration from iMX8MP EVK head file.
Signed-off-by: Ye Li
---
include/configs/imx8mp_evk.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index a6569d5
Enable the EQoS i.MX driver in defconfig, also enable the PHYLIB
to facilitate the case that only has FEC enabled.
Signed-off-by: Ye Li
---
configs/imx8mp_evk_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index
Since SPL has initialized clocks for bus and core. We don't need to
set the default clocks for clock controller node.
Signed-off-by: Ye Li
---
arch/arm/dts/imx8mp-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot
x27;t
become ready (ACMD14 timeout) due to the clock is enabled during
power cycle.
Signed-off-by: Ye Li
Reviewed-by: Haibo Chen
---
drivers/mmc/fsl_esdhc_imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index aa
According to 8MM/MN/MP reference manual, their pad registers only have
4 valid DSE values. And DSE2 and DSE4 are different with current
definitions in iomux-v3.h. Fix the issue to align with manual.
Signed-off-by: Ye Li
Acked-by: Peng Fan
---
arch/arm/include/asm/mach-imx/iomux-v3.h | 21
When send_status is false or wait_dat0 is not supported, the switch
function should not send CMD13 but directly return.
Signed-off-by: Ye Li
---
drivers/mmc/mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8078a89..a1fd533
HS400_ES is missed when down grade to HS mode during
device_remove the mmc device
Signed-off-by: Ye Li
---
drivers/mmc/mmc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index a1fd533..3cb6fda 100644
--- a/drivers/mmc/mmc.c
Since the mxs_nand_spl has implemented adjust read offset in
nand_spl_load_image, so we don't need to check the bad block in
nand_spl_adjust_offset. Directly return the offset to continue
read by nand_spl_load_image.
Signed-off-by: Ye Li
---
drivers/mtd/nand/raw/mxs_nand_spl.c | 5 +
1
When configure the USDHC driver to PIO mode by defining
"CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail.
Two bugs in the driver to cause the issue:
1. The read buffer was invalidated after reading from DATAPORT register,
which should be only applied to DMA mode. The valid data
Thanks, I will change the commit log accordingly.
Best regards,
Ye Li
-Original Message-
From: Stefano Babic [mailto:sba...@denx.de]
Sent: Wednesday, February 19, 2014 9:41 PM
To: Li Ye-B37916; sba...@denx.de; Estevam Fabio-R49496
Cc: u-boot@lists.denx.de; Albert ARIBAUD
Subject: Re
From: "Ye.Li"
When configure the fsl_esdhc driver to PIO mode by defining
"CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail.
Two bugs in the driver to cause the issue:
1. The read buffer was invalidated after reading from DATAPORT register,
which should be only applied to DMA m
From: "Ye.Li"
The load region size of EIM-NOR are defined to 0. For this case,
the parameter "imximage_init_loadsize" must be calculated.
The imximage tool implements the calculation in the "imximage_generate"
function, but the following function "imximage_set_header" resets the value
and not cal
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