Re: [RFC PATCH v2 1/3] Introduce coroutines framework

2025-01-31 Thread Yao Zi
On Tue, Jan 28, 2025 at 11:19:15AM +0100, Jerome Forissier wrote: > Adds the COROUTINES Kconfig symbol which introduces a new internal API > for coroutines support. As explained in the Kconfig file, this is meant > to provide some kind of cooperative multi-tasking with the goal to > improve perform

[RFC PATCH 0/3] Unify implementation of cleanup_before_linux() for RISC-V ports

2025-01-23 Thread Yao Zi
look at the codebase, I think this could be done for all RISC-V ports ultimately. Thanks for your feedback and review. Yao Zi (3): riscv: add a generic implementation for cleanup_before_linux() riscv: cpu: generic: fallback to generic cleanup_before_linux() riscv: cpu: jh7110: fallback to

[RFC PATCH 2/3] riscv: cpu: generic: fallback to generic cleanup_before_linux()

2025-01-23 Thread Yao Zi
The current implementation is equivalent to the fallback one, so this shouldn't change any behaviour but cleans the code up only. Signed-off-by: Yao Zi --- arch/riscv/cpu/generic/Makefile | 1 - arch/riscv/cpu/generic/cpu.c| 22 -- 2 files changed, 23 dele

[RFC PATCH 3/3] riscv: cpu: jh7110: fallback to generic cleanup_before_linux()

2025-01-23 Thread Yao Zi
JH7110 SoC requires no specific handling before entering Linux kernel. Let's drop the specific implementation to avoid duplication. Signed-off-by: Yao Zi --- arch/riscv/cpu/jh7110/Makefile | 1 - arch/riscv/cpu/jh7110/cpu.c| 23 --- 2 files changed, 24 dele

[RFC PATCH 1/3] riscv: add a generic implementation for cleanup_before_linux()

2025-01-23 Thread Yao Zi
Most RISC-V SoCs have similar cleanup_before_linux() functions. Let's provide a weak symbol as fallback to reduce duplicated code. Signed-off-by: Yao Zi --- arch/riscv/cpu/cpu.c | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/

Re: [PATCH] efi_loader: Clean up usage of structure jmp_buf_data

2025-02-16 Thread Yao Zi
On Sat, Feb 15, 2025 at 05:58:18PM +0100, Heinrich Schuchardt wrote: > On 15.02.25 16:54, Yao Zi wrote: > > Structure jmp_buf_data provides the underlying format of jmp_buf, which > > we actually don't care about. Clean up existing code to use the standard > > jmp_bu

[PATCH] efi_loader: Clean up usage of structure jmp_buf_data

2025-02-15 Thread Yao Zi
Structure jmp_buf_data provides the underlying format of jmp_buf, which we actually don't care about. Clean up existing code to use the standard jmp_buf type. This introduces no functional change. Signed-off-by: Yao Zi --- include/efi_loader.h | 4 ++-- lib/efi_loader/efi_boott

Re: Problem with UART in U-Boot.

2025-03-24 Thread Yao Zi
r. > > > > It is necessary to install U-Boot. Can you tell me how to fix the input in > > U-Boot? Version v2025.01. >- 0 ' Thanks, Yao Zi

Re: [PATCH v2 1/3] riscv: image: Add new image type for RV64

2025-04-04 Thread Yao Zi
without inspecting the code around. To me, it sounds more like "RISC-V, but no bitwidth specified". It will be nice if we could avoid this kind of ambiguity. > + IH_ARCH_RISCV64,/* RISC-V 64 bit*/ > IH_ARCH_COUNT, > }; > -- > 2.43.0 > Thanks, Yao Zi

[PATCH 0/2] Fix binman_sym functionality on RISC-V port

2025-04-06 Thread Yao Zi
- qemu-riscv64_defconfig - sifive_unleashed_defconfig - starfive_visionfive2_defconfig with either real hardware or QEMU. Thanks for your time and review. Yao Zi (2): spl: riscv: Disable SPL_BINMAN_UBOOT_SYMBOLS by default riscv: Provide __image_copy_{start_end} symbols in linkerscript arch/riscv/cpu/u-boot-s

[PATCH 1/2] spl: riscv: Disable SPL_BINMAN_UBOOT_SYMBOLS by default

2025-04-06 Thread Yao Zi
sage like Section '/binman/spl-img': Symbol '_binman_u_boot_any_prop_size' in entry '/binman/spl-img/mkimage/u-boot-spl/u-boot-spl-nodtb': Entry 'u-boot-any' not found in list (u-boot-spl-nodtb, u-boot-spl-dtb,u-boot-spl,mkimage,spl-im

[PATCH 2/2] riscv: Provide __image_copy_{start_end} symbols in linkerscript

2025-04-06 Thread Yao Zi
rt in linkerscript of both SPL and proper U-Boot to ensure binman_sym functions correctly with the default binman.dtsi. The paired symbol, __image_copy_end, is introduced as well for completeness. Signed-off-by: Yao Zi --- arch/riscv/cpu/u-boot-spl.lds | 2 ++ arch/riscv/cpu/u-boot.lds | 3 +++ 2

Re: [PATCH 1/2] spl: riscv: Disable SPL_BINMAN_UBOOT_SYMBOLS by default

2025-04-08 Thread Yao Zi
On Mon, Apr 07, 2025 at 10:50:07PM +1200, Simon Glass wrote: > Hi Yao, > > On Mon, 7 Apr 2025 at 15:38, Yao Zi wrote: > > > > The default binman configuration of RISC-V wraps proper U-Boot into a > > FIT image instead of shipping a plain image, thus there's no &

Re: [PATCH 1/2] spl: riscv: Disable SPL_BINMAN_UBOOT_SYMBOLS by default

2025-04-08 Thread Yao Zi
On Mon, Apr 07, 2025 at 01:22:37PM +0200, Jonas Karlman wrote: > Hi, > > On 2025-04-07 05:37, Yao Zi wrote: > > The default binman configuration of RISC-V wraps proper U-Boot into a > > FIT image instead of shipping a plain image, thus there's no > > "u_boot

Re: [PATCH] tools: Fix handle leak in mmap_fdt function

2025-04-18 Thread Yao Zi
44 > --- a/tools/fit_common.c > +++ b/tools/fit_common.c > @@ -123,6 +123,7 @@ err: > close(fd); > if (delete_on_error) > unlink(fname); > + free(ptr); > > return -1; > } > -- > 2.34.1 Thanks, Yao Zi

u-boot@lists.denx.de

2025-04-18 Thread Yao Zi
t;) > Suggested-by: Marek Vasut > Signed-off-by: Heinrich Schuchardt > --- > arch/riscv/dts/jh7110-u-boot.dtsi | 4 > 1 file changed, 4 insertions(+) Tested-by: Yao Zi Sadly this didn't catch up with v2025.04, in which JH7110 SoCs are broken... > diff --git a/

Re: [PATCH v2 1/3] riscv: dts: binman.dtsi: Switch to u-boot-nodtb entry for proper U-Boot

2025-04-17 Thread Yao Zi
On Thu, Apr 17, 2025 at 03:35:50PM -0600, Simon Glass wrote: > Hi Yao, > > On Wed, 16 Apr 2025 at 10:25, Yao Zi wrote: > > > > Switch to u-boot-nodtb entry which precisely represents a proper U-Boot > > and could be matched with u_boot_any. This allows RISC-V ports tha

Re: [PATCH 1/2] Makefile: Strip leading spaces when preprocessing generated_defconfig

2025-04-27 Thread Yao Zi
On Sun, Apr 27, 2025 at 10:16:27AM -0600, Tom Rini wrote: > On Sun, Apr 27, 2025 at 03:46:56PM +0000, Yao Zi wrote: > > On Sun, Apr 27, 2025 at 05:19:04PM +0200, Heinrich Schuchardt wrote: > > > Am 27. April 2025 16:50:10 MESZ schrieb Yao Zi : > > > >Clang's pre

[PATCH 05/10] riscv: dts: th1520: Preserve necessary devices for SPL

2025-04-26 Thread Yao Zi
SPL for TH1520 requires CPU and boot UART nodes to function. Preserve them in SPL devicetree blob with bootph-pre-ram property. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi

[PATCH 06/10] riscv: dts: lichee-module-4a: Preserve memory node for SPL

2025-04-26 Thread Yao Zi
Memory node is necessary for TH1520 SPL to configure size and base address of DRAM. Let's preserve it in SPL devicetree blob. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dt

Re: Build for RISC-V with LLVM

2025-04-26 Thread Yao Zi
On Sat, Apr 26, 2025 at 06:25:50PM -0500, Nathaniel wrote: > On Apr 26 2025, at 1:30 am, Yao Zi wrote: > > On Fri, Apr 25, 2025 at 12:43:08PM -0500, Nathaniel Hourt wrote: > > > Hi, all > > > > > > I am trying to build u-boot and SPL for my Mars board (riscv,

[PATCH 0/2] Clang compatibility improvements for RISC-V

2025-04-27 Thread Yao Zi
used for now. To test the changes on JH7110 platforms, this patch[2] must be applied for SPL to function. [1]: https://lore.kernel.org/u-boot/932979cb47c4fded7ac19216ca172...@nathaniel.land/ [2]: https://lore.kernel.org/all/20250330162421.238483-1-heinrich.schucha...@canonical.com/ Yao

[PATCH 2/2] riscv: Access gd with inline assembly when building with LTO or Clang

2025-04-27 Thread Yao Zi
aking RISC-V ports function properly and preparing for introduction of LTO in the future. Board initialization code is also adapted for non-assignable gd. Reported-by: Nathaniel Hourt Signed-off-by: Yao Zi --- arch/riscv/cpu/cpu.c | 6 ++ arch/riscv/include/asm/global_data.h

[PATCH 1/2] Makefile: Strip leading spaces when preprocessing generated_defconfig

2025-04-27 Thread Yao Zi
Nathaniel Hourt Signed-off-by: Yao Zi --- scripts/kconfig/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index 079add4d5da..ba30652f01a 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -94,6 +94,7 @@ end

Re: [PATCH 1/2] Makefile: Strip leading spaces when preprocessing generated_defconfig

2025-04-27 Thread Yao Zi
On Sun, Apr 27, 2025 at 05:19:04PM +0200, Heinrich Schuchardt wrote: > Am 27. April 2025 16:50:10 MESZ schrieb Yao Zi : > >Clang's preprocessor may emit extra spaces for lines starting with '#'. > >Lines with these extra characters cannot be handled by Kconfig and wi

Re: [PATCH 2/2] riscv: Provide __image_copy_{start_end} symbols in linkerscript

2025-04-10 Thread Yao Zi
On Mon, Apr 07, 2025 at 01:10:32PM +0200, Jonas Karlman wrote: > Hi, > > On 2025-04-07 05:37, Yao Zi wrote: > > Binman looks for __image_copy_start to determine the base address of an > > entry if elf-base-sym isn't specified, which is missing in RISC-V port. > >

[PATCH v2 0/3] Fix binman_sym functionality on RISC-V port

2025-04-16 Thread Yao Zi
d patch to prevent binman from relocating SPL of VisionFive 2 - Fix typo (one missing underscore) in linkerscript and collect Simon's r-b tag. - Link to v1: https://lore.kernel.org/u-boot/20250407033744.4025-1-zi...@disroot.org/ Yao Zi (3): riscv: dts: binman.dtsi: Switch to u-boot-nodtb

[PATCH v2 2/3] riscv: dts: starfive: Prevent binman from relocating symbols in SPL

2025-04-16 Thread Yao Zi
7;/binman/spl-img/mkimage/u-boot-spl/u-boot-spl-nodtb': Entry 'u-boot-any' not found in list (u-boot-spl-nodtb, u-boot-spl-dtb,u-boot-spl,mkimage,spl-img) Fixes: 90602e779d3 ("riscv: dts: starfive: generate u-boot-spl.bin.normal.out") Suggested-by: Jonas K

[PATCH v2 3/3] riscv: Provide __image_copy_{start_end} symbols in linkerscript

2025-04-16 Thread Yao Zi
rt in linkerscript of both SPL and proper U-Boot to ensure binman_sym functions correctly with the default binman.dtsi. The paired symbol, __image_copy_end, is introduced as well for completeness. Signed-off-by: Yao Zi Reviewed-by: Simon Glass --- arch/riscv/cpu/u-boot-spl.lds | 2 ++ arch/riscv/

[PATCH v2 1/3] riscv: dts: binman.dtsi: Switch to u-boot-nodtb entry for proper U-Boot

2025-04-16 Thread Yao Zi
ifive: unleashed: Switch to use binman to generate u-boot.itb") Suggested-by: Jonas Karlman Signed-off-by: Yao Zi --- arch/riscv/dts/binman.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 0405faca574..b7656423

Re: Build for RISC-V with LLVM

2025-05-01 Thread Yao Zi
On Thu, May 01, 2025 at 03:54:34PM -0500, Nathaniel Hourt wrote: > On 2025-04-26 23:34, Yao Zi wrote: > > On Sat, Apr 26, 2025 at 06:25:50PM -0500, Nathaniel wrote: > > > On Apr 26 2025, at 1:30 am, Yao Zi wrote: > > > > On Fri, Apr 25, 2025 at 12:43:08P

Re: [GIT PULL] u-boot-riscv/master

2025-04-25 Thread Yao Zi
five: use consistent formatting > doc: starfive: use jh7110_common.rst > doc: jh7110: describe debug UART > > Huan Zhou (2): > riscv: dts: k1: add pinctrl property in dts. > config: Enable pinctrl in bananapi-f3 > > Minda Chen (1): > MAINT

Re: [PATCH 1/2] Makefile: Strip leading spaces when preprocessing generated_defconfig

2025-04-29 Thread Yao Zi
On Mon, Apr 28, 2025 at 08:49:43AM -0600, Tom Rini wrote: > On Mon, Apr 28, 2025 at 03:57:27AM +0000, Yao Zi wrote: > > On Sun, Apr 27, 2025 at 10:16:27AM -0600, Tom Rini wrote: > > > On Sun, Apr 27, 2025 at 03:46:56PM +, Yao Zi wrote: > > > > On Sun, Apr 27, 2025

Re: Build for RISC-V with LLVM

2025-04-25 Thread Yao Zi
e board. If I pass a working SPL Have you tried to apply this patch[1]? U-Boot support for JH7110 is broken at least in v2025.04 release afaik. Best regards, Yao Zi [1]: https://lore.kernel.org/all/20250330162421.238483-1-heinrich.schucha...@canonical.com/ > I downloaded, it logs some output

[PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520

2025-04-26 Thread Yao Zi
16GiB variants of LicheePi 4A boards and I could test with. Support for other configurations could be easily added later. Link: https://github.com/ziyao233/th1520-firmware # [1] Signed-off-by: Yao Zi --- drivers/ram/Kconfig| 1 + drivers/ram/Makefile | 4 + drivers/ram

[PATCH 09/10] board: thead: licheepi4a: Enable SPL support

2025-04-26 Thread Yao Zi
Adjust Kconfig and defconfig and add SPL initialization code for Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC earlier. The board devicetree is changed to use TH1520 binman configuration to generate bootable images. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520-l

[PATCH 10/10] doc: thead: lpi4a: Update documentation

2025-04-26 Thread Yao Zi
Support for eMMC, SD card, GPIO and SPL have been available in LPi4A port. Update the documentation of support status and build instructions. Signed-off-by: Yao Zi --- doc/board/thead/lpi4a.rst | 58 +-- 1 file changed, 55 insertions(+), 3 deletions(-) diff

[PATCH 07/10] riscv: dts: th1520: Add DRAM controller

2025-04-26 Thread Yao Zi
Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL devicetree blob. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index ef84d8cc265..b908eb37e41

[PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520

2025-04-26 Thread Yao Zi
16GiB variants of LicheePi 4A boards and I could test with. Support for other configurations could be easily added later. Link: https://github.com/ziyao233/th1520-firmware # [1] Signed-off-by: Yao Zi --- drivers/ram/Kconfig| 1 + drivers/ram/Makefile | 4 + drivers/ram

[PATCH 03/10] riscv: cpu: Add TH1520 CPU support

2025-04-26 Thread Yao Zi
Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi --- arch/riscv/Kconfig

[PATCH 01/10] riscv: lib: Split out support for T-Head cache management operations

2025-04-26 Thread Yao Zi
, allowing SoCs shipping T-Head cores to share the code. Link: https://github.com/XUANTIE-RV/thead-extension-spec Signed-off-by: Yao Zi --- arch/riscv/Kconfig | 8 arch/riscv/cpu/cv1800b/Kconfig | 1 + arch/riscv/cpu/cv1800b/Makefile

[PATCH 00/10] Initial SPL support for T-Head TH1520 SoC

2025-04-26 Thread Yao Zi
. [1]: https://lore.kernel.org/all/20250416162533.1396-1-zi...@disroot.org/ Yao Zi (10): riscv: lib: Split out support for T-Head cache management operations riscv: dts: th1520: Add clock-frequency for UART0 riscv: cpu: Add TH1520 CPU support ram: thead: Add initial DDR controller support for TH

[PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0

2025-04-26 Thread Yao Zi
The BROM of TH1520 always initializes its clock and configure the baudrate to 115200. Add a clock-frequency property to provide such information without introducing CCF to SPL. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv

Re: [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520

2025-04-26 Thread Yao Zi
On Sat, Apr 26, 2025 at 04:56:58PM +, Yao Zi wrote: > This patch cleans the vendor code of DDR initialization up, converts the > driver to fit in DM framework and use a firmware[1] packaged by binman to > ship PHY configuration. > > Currently the driver is only capable of i

[PATCH 08/10] riscv: dts: th1520: Add binman configuration

2025-04-26 Thread Yao Zi
Add binman configuration for TH1520 SoC, whose BROM loads the image combined into SRAM and directly jumps to it. The configuration creates u-boot-with-spl.bin where the SPL code locates at the start and the DDR firmware is shipped. Signed-off-by: Yao Zi --- arch/riscv/dts/thead-th1520

[PATCH] riscv: dts: binman.dtsi: Drop filename property for proper U-Boot

2025-04-26 Thread Yao Zi
Drop filename property for proper U-Boot entry since binman takes "u-boot-nodtb.bin" as the default filename for u-boot-nodtb entries. This follows efe9c12322b ("riscv: dts: binman.dtsi: Switch to u-boot-nodtb entry for proper U-Boot") to clean binman.dtsi up. Signed-off-by:

Re: [PATCH 2/5] arm: include asm-generic/int-ll64.h in setjmp.h

2025-03-02 Thread Yao Zi
On Sun, Mar 02, 2025 at 05:18:21PM +0100, Heinrich Schuchardt wrote: > Yao Zi schrieb am So., 2. März 2025, 17:02: > > > On Sun, Mar 02, 2025 at 03:21:18PM +0100, Heinrich Schuchardt wrote: > > > Don't assume that u32 and u64 are already defined. > > > >

Re: [PATCH 2/5] arm: include asm-generic/int-ll64.h in setjmp.h

2025-03-02 Thread Yao Zi
; * This really should be opaque, but the EFI implementation wrongly > * assumes that a 'struct jmp_buf_data' is defined. With PATCH 4 of the series, this comment isn't true anymore. Should we fix it up at the same time? > -- > 2.48.1 > Best regards, Yao Zi

[PATCH v2 2/4] board: qemu: riscv: Remove duplicated board_fdt_blob_setup

2025-03-07 Thread Yao Zi
The default version should work for RISC-V QEMU. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- board/emulation/qemu-riscv/qemu-riscv.c | 8 1 file changed, 8 deletions(-) diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index

[PATCH v2 3/4] board: starfive: Remove duplicated board_fdt_blob_setup

2025-03-07 Thread Yao Zi
The default version should work for Starfive VisionFive 2. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- board/starfive/visionfive2/starfive_visionfive2.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board

[PATCH v2 1/4] riscv: lib: Add a default implementation of board_fdt_blob_setup

2025-03-07 Thread Yao Zi
It's common for S-Mode proper U-Boot to retrieve a FDT blob along with taking control from SBI firmware. Add a weak version of board_fdt_blob_setup to make use of it by default, avoiding copy-pasting similar functions among boards. Signed-off-by: Yao Zi --- arch/riscv/lib/Makefile | 1 +

[PATCH v2 0/4] Simplify retrieving FDT from SBI in S-Mode

2025-03-07 Thread Yao Zi
orm chagnes - don't enable OF_HAS_PRIOR_STAGE by default on all SBI-capable RISC-V platforms, as it may break the binman configuration - Link to v1: https://lore.kernel.org/u-boot/20250227144734.61458-1-zi...@disroot.org/ Yao Zi (4): riscv: lib: Add a default implementation of boar

Re: [PATCH 5/5] riscv: select OF_HAS_PRIOR_STAGE by default if SBI is enabled

2025-03-07 Thread Yao Zi
On Thu, Mar 06, 2025 at 07:09:06PM +0800, Leo Liang wrote: > On Thu, Feb 27, 2025 at 02:47:33PM +0000, Yao Zi wrote: > > Availability of RISC-V SBI service implies a prior stage exists. As SBI > > firmware usually passes a FDT to the loaded program, let's select > > OF

[PATCH v2 4/4] board: sifive: Remove dead board_fdt_blob_setup

2025-03-07 Thread Yao Zi
CONFIG_OF_BOARD isn't enabled on SiFive Unleashed and Unmatched, thus board_fdt_blob_setup is actually dead code on these platforms. Let's remove it. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- board/sifive/unleashed/unleashed.c | 11 --- board/sifive/unmatched/u

Re: [GIT PULL] u-boot-riscv/master

2025-03-07 Thread Yao Zi
figuration for MULTI_DTB_FIT > board: starfive: spl: strip off 'starfive/' prefix > riscv: dts: starfive: remove duplicate itb entries > > Junhui Liu (1): > riscv: dts: spacemit: Update UART compatible for k1 > > Yao Zi (4): > riscv: lib

[PATCH] clk: sophgo: Fix return values of register updating helpers

2025-03-07 Thread Yao Zi
lk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC") Tested-by: Yuguo Pei Signed-off-by: Yao Zi --- drivers/clk/sophgo/clk-common.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sophgo/clk-common.h b/drivers/clk/sophgo/clk-common.h in

[PATCH] riscv: dts: cv18xx: Drop unused dummy clocks

2025-03-07 Thread Yao Zi
Introduced in commit 5a4e0625ac77 ("riscv: dts: sophgo: Add ethernet node"), eth_{csrclk,ptpclk} were used as placeholders for ethernet controller. As the real clock controller has been added, drop them to clean the devicetree up. Signed-off-by: Yao Zi --- arch/riscv/dts/cv18xx

Re: Building separate SPL with U-boot

2025-03-08 Thread Yao Zi
> Regards, > Ali Best regards, Yao Zi

Re: [PATCH 5/5] riscv: select OF_HAS_PRIOR_STAGE by default if SBI is enabled

2025-03-06 Thread Yao Zi
On Thu, Mar 06, 2025 at 07:09:06PM +0800, Leo Liang wrote: > On Thu, Feb 27, 2025 at 02:47:33PM +0000, Yao Zi wrote: > > Availability of RISC-V SBI service implies a prior stage exists. As SBI > > firmware usually passes a FDT to the loaded program, let's select > > OF

Re: [PATCH v2 08/14] lib: time: hook uthread_schedule() into udelay()

2025-02-28 Thread Yao Zi
by constantly scheduling new tasks? Perhaps we > should at least leave the task running for some time? If I get the point, the UTHREAD is a cooperative framework, which means a task yields the control flow only when it considers nothing else could be done. And

[PATCH 0/5] Simplifiy retrieving FDT from SBI in S-Mode

2025-02-27 Thread Yao Zi
duplication. We also select OF_HAS_PRIOR_STAGE by default on RISC-V platforms if SBI is enabled, which is the usual configuration. Tested on - Milk-V Duo (milkv_duo_defconfig) - Starfive VisionFive 2 (starfive_visionfive2_defconfig) - QEMU VM (qemu-riscv64_smode_defconfig). Yao Zi (5): riscv:

[PATCH 2/5] board: qemu: riscv: Remove duplicated board_fdt_blob_setup

2025-02-27 Thread Yao Zi
The default version should work for RISC-V QEMU. Signed-off-by: Yao Zi --- board/emulation/qemu-riscv/qemu-riscv.c | 8 1 file changed, 8 deletions(-) diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index a90222ea6a4..70190ebe8fc 100644

[PATCH 5/5] riscv: select OF_HAS_PRIOR_STAGE by default if SBI is enabled

2025-02-27 Thread Yao Zi
fault. This covers the most common usecase, where a SPL (probably the U-Boot one) selects proper devicetree, loads SBI and U-Boot then invokes SBI with the devicetree. Signed-off-by: Yao Zi --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kc

[PATCH 1/5] riscv: lib: Add a default implementation of board_fdt_blob_setup

2025-02-27 Thread Yao Zi
It's common for S-Mode U-Boot to retrieve a FDT blob along with taking control from SBI firmware. Add a weak version of board_fdt_blob_setup to make use of it by default and avoid copy-pasting similar functions among boards. Signed-off-by: Yao Zi --- arch/riscv/lib/Makefile | 1 + arch/

[PATCH 4/5] board: sifive: Remove duplicated board_fdt_blob_setup

2025-02-27 Thread Yao Zi
The default version should work for both SiFive Unmatched and Unleashed. Signed-off-by: Yao Zi --- board/sifive/unleashed/unleashed.c | 11 --- board/sifive/unmatched/unmatched.c | 10 -- 2 files changed, 21 deletions(-) diff --git a/board/sifive/unleashed/unleashed.c b/board

[PATCH 3/5] board: starfive: Remove duplicated board_fdt_blob_setup

2025-02-27 Thread Yao Zi
The default version should work for Starfive VisionFive 2. Signed-off-by: Yao Zi --- board/starfive/visionfive2/starfive_visionfive2.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2

Re: [RFC PATCH 06/10] uthread: add cooperative multi-tasking interface

2025-02-14 Thread Yao Zi
"Default uthread stack size" > + depends on UTHREAD > + default 32168 Why choose 32168? It's even not a power of two. Typo for 32768? > + help > + The default stask size for uthreads. Each uthread has its own stack. > + > endmenu > > source "lib/fwu_updates/Kconfig" Thanks, Yao Zi

Re: [RFC PATCH 10/10] test: lib: add uthread test

2025-02-14 Thread Yao Zi
list_del(&next->list); > uthread_free(next); > } I think this should belong to the sixth patch. > diff --git a/test/lib/Makefile b/test/lib/Makefile > index bf04685dae1..c991dff1c63 100644 > --- a/test/lib/Makefile > +++ b/test/lib/Makefile > ... Best regards, Yao Zi

Re: [PATCH] efi_loader: Clean up usage of structure jmp_buf_data

2025-02-16 Thread Yao Zi
On Sun, Feb 16, 2025 at 05:50:53PM +0100, Heinrich Schuchardt wrote: > Am 16. Februar 2025 15:26:31 MEZ schrieb Yao Zi : > >On Sat, Feb 15, 2025 at 05:58:18PM +0100, Heinrich Schuchardt wrote: > >> On 15.02.25 16:54, Yao Zi wrote: > >> > Structure jmp_buf_data pro

[PATCH] riscv: timer: Add thead,c900-clint compatible

2025-02-20 Thread Yao Zi
running in S-Mode isn't necessary for the driver to operate, Kconfig and comments are also adapted to avoid confusion. Reference: https://github.com/riscv-software-src/opensbi/commit/ca7810aecdba Signed-off-by: Yao Zi --- This is necessary for several platforms based on T-Head C9xx to get s

Re: [PATCH] riscv: timer: Add thead,c900-clint compatible

2025-02-20 Thread Yao Zi
On Thu, Feb 20, 2025 at 10:31:53AM +, Yao Zi wrote: > Current implementation of riscv_timer.c only assumes readable TIMER CSRs > present (IOW, Zicntr extension is available). Core Local Interruptors > (CLINT) found on T-Head C9xx cores expose its mtime register through > TIME

[PATCH v2 08/10] riscv: dts: th1520: Add binman configuration

2025-05-13 Thread Yao Zi
Add binman configuration for TH1520 SoC, whose BROM loads the image combined into SRAM and directly jumps to it. The configuration creates u-boot-with-spl.bin where the SPL code locates at the start and the DDR firmware is shipped. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch

[PATCH v2 06/10] riscv: dts: lichee-module-4a: Preserve memory node for SPL

2025-05-13 Thread Yao Zi
Memory node is necessary for TH1520 SPL to configure size and base address of DRAM. Let's preserve it in SPL devicetree blob. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/risc

[PATCH v2 09/10] board: thead: licheepi4a: Enable SPL support

2025-05-13 Thread Yao Zi
Adjust Kconfig and defconfig and add SPL initialization code for Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC earlier. The board devicetree is changed to use TH1520 binman configuration to generate bootable images. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi

[PATCH v2 10/10] doc: thead: lpi4a: Update documentation

2025-05-13 Thread Yao Zi
Support for eMMC, SD card, GPIO and SPL have been available in LPi4A port. Update the documentation of support status and build instructions. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- doc/board/thead/lpi4a.rst | 58 +-- 1 file changed, 55

[PATCH v2 00/10] Initial SPL support for T-Head TH1520 SoC

2025-05-13 Thread Yao Zi
a.h for SPL. - Add missing SPDX and copyright header for the DDR driver. - Link to v1: https://lore.kernel.org/all/20250426165704.35523-1-zi...@disroot.org/ Yao Zi (10): riscv: lib: Split out support for T-Head cache management operations configs: th1520_lpi4a: Add UART clock frequency riscv

[PATCH v2 01/10] riscv: lib: Split out support for T-Head cache management operations

2025-05-13 Thread Yao Zi
, allowing SoCs shipping T-Head cores to share the code. Link: https://github.com/XUANTIE-RV/thead-extension-spec Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 8 arch/riscv/cpu/cv1800b/Kconfig | 1 + arch

[PATCH v2 02/10] configs: th1520_lpi4a: Add UART clock frequency

2025-05-13 Thread Yao Zi
The BROM of TH1520 always initializes UART0's parent clock and configures the baudrate to 115200. Describe the clock frequency to make UART function correctly in SPL without introducing CCF. Signed-off-by: Yao Zi --- include/configs/th1520_lpi4a.h | 1 + 1 file changed, 1 insertion(+)

[PATCH v2 03/10] riscv: cpu: Add TH1520 CPU support

2025-05-13 Thread Yao Zi
Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi

[PATCH v2 04/10] ram: thead: Add initial DDR controller support for TH1520

2025-05-13 Thread Yao Zi
16GiB variants of LicheePi 4A boards and I could test with. Support for other configurations could be easily added later. Link: https://github.com/ziyao233/th1520-firmware # [1] Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- drivers/ram/Kconfig| 1 + drivers/ram/Makefile

[PATCH v2 05/10] riscv: dts: th1520: Preserve necessary devices for SPL

2025-05-13 Thread Yao Zi
SPL for TH1520 requires CPU and boot UART nodes to function. Preserve them in SPL devicetree blob with bootph-pre-ram property. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/th1520.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/dts/th1520

Re: [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0

2025-05-12 Thread Yao Zi
On Mon, May 12, 2025 at 07:53:01AM -0400, e wrote: > On 2025-05-12 05:57, Leo Liang wrote: > > On Sat, Apr 26, 2025 at 04:56:56PM +0000, Yao Zi wrote: > > > [EXTERNAL MAIL] > > > > > > The BROM of TH1520 always initializes its clock and configure the &

[PATCH v2 07/10] riscv: dts: th1520: Add DRAM controller

2025-05-13 Thread Yao Zi
Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL devicetree blob. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/th1520.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi

[PATCH 2/4] clk: thead: Port clock controller driver of TH1520 SoC

2025-05-15 Thread Yao Zi
igned-off-by: Yao Zi --- drivers/clk/Kconfig |1 + drivers/clk/Makefile |1 + drivers/clk/thead/Kconfig | 19 + drivers/clk/thead/Makefile|5 + drivers/clk/thead/clk-th1520-ap.c | 1031 + 5 files changed,

[PATCH 3/4] riscv: cpu: th1520: Select clock driver

2025-05-15 Thread Yao Zi
The clock driver is essential for TH1520 SoCs to operate. Select the driver in SoC Kconfig entry. Signed-off-by: Yao Zi --- arch/riscv/cpu/th1520/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig index a916d364e6c

[PATCH 4/4] riscv: dts: th1520: Complete clock tree

2025-05-15 Thread Yao Zi
Describe the newly-supported clock controller of TH1520 in SoC devicetree, replace dummy clocks with the controller-supplied ones and add correct clocks for GPIO controllers. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520-lichee-module-4a.dtsi | 8 --- arch/riscv/dts/th1520.dtsi

[PATCH 1/4] riscv: cpu: th1520: Initialize IOPMPs in SPL

2025-05-15 Thread Yao Zi
TH1520 SoC ships several IOPMPs protecting various on-chip peripherals. They must be configured before accessing the peripherals. Let's initialize them in SPL harts_early_init(). Signed-off-by: Yao Zi --- arch/riscv/cpu/th1520/spl.c| 65 ++ arch/riscv/in

[PATCH 0/4] Improve usability of TH1520 with mainline SPL

2025-05-15 Thread Yao Zi
ld be obtained here[2]. Thanks for your time and review. [1]: https://lore.kernel.org/all/20250513090503.46670-1-zi...@disroot.org/ [2]: https://gist.github.com/ziyao233/75ff1e5b2cf9161093fcc12ed0a62395 Yao Zi (4): riscv: cpu: th1520: Initialize IOPMPs in SPL clk: thead: Port clock controller driv

Re: [GIT PULL] u-boot-riscv/master

2025-05-22 Thread Yao Zi
t; I'll consider IH_ARCH_RISCV32 a better idea, instead of implying 32bit > when no suffix attached. We (and the Linux kernel) mix 32-bit and 64-bit > variants of RISC-V together, thus it's hard to tell the exact bitwidth > of "IH_ARCH_RISCV" without inspecting the code around. To me, it sounds > more like "RISC-V, but no bitwidth specified". > > It will be nice if we could avoid this kind of ambiguity. (referring my own reply[1]) I'll second explicit 32-bit and 64-bit entries, and keeping IH_ARCH_RISCV for compatibility consideration. > > Hopefully my lack of bisection isn't causing me to blame something > incorrect, but I'll go try to replicate now :) Regards, Yao Zi [1]: https://lore.kernel.org/u-boot/z_cjtyxavrpuo...@pie.lan/

[PATCH] ram: Move Kconfig options into their own menu entry

2025-06-02 Thread Yao Zi
ate a menu entry for these drivers. Fixes: 6c51df6859f ("dm: Add support for RAM drivers") Signed-off-by: Yao Zi --- drivers/ram/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 39d03e8d3d3..edb8e254d5b 100644 --- a/drivers/ra

Re: [PATCH] scripts/spelling.txt: Sync script with kernel v6.15

2025-05-30 Thread Yao Zi
On Fri, May 30, 2025 at 08:05:48AM -0600, Tom Rini wrote: > Keep spelling.txt in sync with the version from kernel v6.15. > > Reported-by: Yao Zi > Signed-off-by: Tom Rini > --- > Cc: Heinrich Schuchardt > > Heinrich, adding 'volatge' here makes sense, but

[PATCH 1/3] pinctrl: Port pin controller driver for T-Head TH1520 SoC

2025-06-18 Thread Yao Zi
configure are specfied as strings and looked up at runtime, which the generic pinctrl helpers of U-Boot cannot parse, thus a customized set_state() callback is implemented to parse pinconfig nodes and setup the configuration. Signed-off-by: Yao Zi --- MAINTAINERS | 1 + drivers

[PATCH 0/3] Add pinctrl support for TH1520 SoC

2025-06-18 Thread Yao Zi
s on Lichee Pi 4A"[1] for a clean apply. An output of pinmux status -a could be obtained here[2]. [1]: https://lore.kernel.org/u-boot/20250606042804.64311-1-zi...@disroot.org/ [2]: https://gist.github.com/ziyao233/55738ed1a33d450ccb1dc3752494a2b4 Yao Zi (3): pinctrl: Port pin controller dri

[PATCH 2/3] riscv: dts: th1520: Add pin controllers

2025-06-18 Thread Yao Zi
Describe the three pin controllers integrated in TH1520 SoC. Since we don't have support for clocks in the AON region, a dummy fixed-clock node is added to supply the pin controller locating in it. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520.dtsi | 28 1

[PATCH 3/3] riscv: cpu: th1520: Enable pinctrl by default

2025-06-18 Thread Yao Zi
Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for existing TH1520-based boards to ensure PINCTRL is enabled. Signed-off-by: Yao Zi --- arch/riscv/cpu/th1520/Kconfig | 1 + configs/th1520_lpi4a_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/cpu

Re: [PULL] u-boot-riscv/next

2025-06-07 Thread Yao Zi
-riscv/-/pipelines/26483 > > > > - board: Convert Lichee Pi 4A to use S-Mode proper U-Boot > > - RISC-V: configs: Raise SPL_SYS_MALLOC_SIZE to 8 MiB > > - driver: Add SD card support to the Beagle-V-Fire >

[PATCH 3/5] riscv: cpu: th1520: Add a routine to bring up secondary cores

2025-06-05 Thread Yao Zi
On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by hardware, and the remaining HARTs are in reset states, requiring manual setup of reset address and deassertion to function normal. Introduce a routine to do the work. Signed-off-by: Yao Zi --- arch/riscv/cpu/th1520/cpu.c

[PATCH 4/5] riscv: dts: th1520: Preserve CLINT node for SPL

2025-06-05 Thread Yao Zi
Preserve CLINT node for SPL, whose IPI functionality is essential for operation of a multi-core system. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index 28107a9f354..e773d2e6a80

[PATCH 5/5] board: thead: licheepi4a: Bring up secondary cores in SPL

2025-06-05 Thread Yao Zi
Setup core information and bring secondary HARTs up for a functional multi-core system. Signed-off-by: Yao Zi --- board/thead/th1520_lpi4a/spl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c index 25dfa387c36..d75fa6f3eff

[PATCH 2/5] riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init

2025-06-05 Thread Yao Zi
. Signed-off-by: Yao Zi --- arch/riscv/cpu/th1520/spl.c | 83 + 1 file changed, 83 insertions(+) diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c index 362fe895f86..b95470485f6 100644 --- a/arch/riscv/cpu/th1520/spl.c +++ b/arch/riscv/cpu

  1   2   >