This series adds initial SPL support for T-Head TH1520 SoC and Sipeed Lichee Pi 4A board. Key changes include,
- Support for T-Head-specific cache management operations is split out of CV1800B port and adapted for usage in other ports. - A new CPU target, THEAD_TH1520, is added with SPL support enabled. - Driver for TH1520's DDR controller is cleaned up from the vendor U-Boot source. - For building the bootable image, of which TH1520's BROM executes from the start, from SPL, DDR firmware and proper U-Boot, a binman configuration for TH1520 is added. Note that the binman configuration doesn't inherit the default one for RISC-V, as our proper U-Boot runs in M-Mode and reusing riscv/dts/binman.dtsi doesn't help much. Tested on the 16GiB variant of Sipeed Lichee Pi 4A. Loading u-boot-with-spl.bin to SRAM with fastboot through BROM, I've successfully booted into U-Boot console with DRAM initialized. This series is based on the latest master branch. Thanks for your time and review. Changed from v1 - Remove patch "riscv: dts: th1520: Add clock-frequency for UART0", UART clocks are now described with CFG_SYS_NS16550_CLK in th1520_lpi4a.h for SPL. - Add missing SPDX and copyright header for the DDR driver. - Link to v1: https://lore.kernel.org/all/20250426165704.35523-1-zi...@disroot.org/ Yao Zi (10): riscv: lib: Split out support for T-Head cache management operations configs: th1520_lpi4a: Add UART clock frequency riscv: cpu: Add TH1520 CPU support ram: thead: Add initial DDR controller support for TH1520 riscv: dts: th1520: Preserve necessary devices for SPL riscv: dts: lichee-module-4a: Preserve memory node for SPL riscv: dts: th1520: Add DRAM controller riscv: dts: th1520: Add binman configuration board: thead: licheepi4a: Enable SPL support doc: thead: lpi4a: Update documentation arch/riscv/Kconfig | 9 + arch/riscv/cpu/cv1800b/Kconfig | 1 + arch/riscv/cpu/cv1800b/Makefile | 1 - arch/riscv/cpu/th1520/Kconfig | 21 + arch/riscv/cpu/th1520/Makefile | 8 + arch/riscv/cpu/th1520/cache.c | 32 + arch/riscv/cpu/th1520/cpu.c | 21 + arch/riscv/cpu/th1520/dram.c | 21 + arch/riscv/cpu/th1520/spl.c | 31 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 + arch/riscv/dts/th1520-lichee-pi-4a.dts | 1 + arch/riscv/dts/th1520.dtsi | 16 + arch/riscv/dts/thead-th1520-binman.dtsi | 55 ++ arch/riscv/include/asm/arch-th1520/cpu.h | 9 + arch/riscv/include/asm/arch-th1520/spl.h | 10 + arch/riscv/lib/Makefile | 1 + .../{cpu/cv1800b/cache.c => lib/thead_cmo.c} | 0 board/thead/th1520_lpi4a/Kconfig | 5 +- board/thead/th1520_lpi4a/Makefile | 1 + board/thead/th1520_lpi4a/spl.c | 48 ++ configs/th1520_lpi4a_defconfig | 18 + doc/board/thead/lpi4a.rst | 58 +- drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 4 + drivers/ram/thead/Kconfig | 5 + drivers/ram/thead/Makefile | 1 + drivers/ram/thead/th1520_ddr.c | 787 ++++++++++++++++++ include/configs/th1520_lpi4a.h | 1 + 28 files changed, 1161 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/cpu/th1520/Kconfig create mode 100644 arch/riscv/cpu/th1520/Makefile create mode 100644 arch/riscv/cpu/th1520/cache.c create mode 100644 arch/riscv/cpu/th1520/cpu.c create mode 100644 arch/riscv/cpu/th1520/dram.c create mode 100644 arch/riscv/cpu/th1520/spl.c create mode 100644 arch/riscv/dts/thead-th1520-binman.dtsi create mode 100644 arch/riscv/include/asm/arch-th1520/cpu.h create mode 100644 arch/riscv/include/asm/arch-th1520/spl.h rename arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} (100%) create mode 100644 board/thead/th1520_lpi4a/spl.c create mode 100644 drivers/ram/thead/Kconfig create mode 100644 drivers/ram/thead/Makefile create mode 100644 drivers/ram/thead/th1520_ddr.c -- 2.49.0
