Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,
- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL
Signed-off-by: Yao Zi <zi...@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com>
---
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/th1520/Kconfig | 21 ++++++++++++++++
arch/riscv/cpu/th1520/Makefile | 8 ++++++
arch/riscv/cpu/th1520/cache.c | 32 ++++++++++++++++++++++++
arch/riscv/cpu/th1520/cpu.c | 21 ++++++++++++++++
arch/riscv/cpu/th1520/dram.c | 21 ++++++++++++++++
arch/riscv/cpu/th1520/spl.c | 31 +++++++++++++++++++++++
arch/riscv/include/asm/arch-th1520/cpu.h | 9 +++++++
arch/riscv/include/asm/arch-th1520/spl.h | 10 ++++++++
9 files changed, 154 insertions(+)
create mode 100644 arch/riscv/cpu/th1520/Kconfig
create mode 100644 arch/riscv/cpu/th1520/Makefile
create mode 100644 arch/riscv/cpu/th1520/cache.c
create mode 100644 arch/riscv/cpu/th1520/cpu.c
create mode 100644 arch/riscv/cpu/th1520/dram.c
create mode 100644 arch/riscv/cpu/th1520/spl.c
create mode 100644 arch/riscv/include/asm/arch-th1520/cpu.h
create mode 100644 arch/riscv/include/asm/arch-th1520/spl.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index dc36d9b8566..8c6feae5735 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -126,6 +126,7 @@ source "arch/riscv/cpu/generic/Kconfig"
source "arch/riscv/cpu/jh7110/Kconfig"
source "arch/riscv/cpu/k1/Kconfig"
source "arch/riscv/cpu/k230/Kconfig"
+source "arch/riscv/cpu/th1520/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig
new file mode 100644
index 00000000000..a916d364e6c
--- /dev/null
+++ b/arch/riscv/cpu/th1520/Kconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng...@gmail.com>
+# Copyright (C) 2025, Yao Zi <zi...@disroot.org>
+
+config THEAD_TH1520
+ bool
+ select ARCH_EARLY_INIT_R
+ select SYS_CACHE_SHIFT_6
+ select SUPPORT_SPL
+ select BINMAN if SPL
+ select SYS_CACHE_THEAD_CMO
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply RISCV_ACLINT if RISCV_MMODE
+ imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
+ imply CMD_CPU
+ imply SPL_CPU
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/th1520/Makefile b/arch/riscv/cpu/th1520/Makefile
new file mode 100644
index 00000000000..5d806c06e2e
--- /dev/null
+++ b/arch/riscv/cpu/th1520/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025, Yao Zi <zi...@disroot.org>
+
+obj-y += cache.o
+obj-y += cpu.o
+obj-y += dram.o
+obj-y += spl.o
diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c
new file mode 100644
index 00000000000..08aa1f789fd
--- /dev/null
+++ b/arch/riscv/cpu/th1520/cache.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Yao Zi <zi...@disroot.org>
+ */
+
+#include <asm/io.h>
+#include <cpu_func.h>
+#include <linux/bitops.h>
+
+#define CSR_MHCR 0x7c1
+#define CSR_MHCR_IE BIT(0)
+#define CSR_MHCR_DE BIT(1)
+
+void icache_enable(void)
+{
+ csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
+}
+
+void dcache_enable(void)
+{
+ csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_DE);
+}
+
+int icache_status(void)
+{
+ return (csr_read(CSR_MHCR) & CSR_MHCR_IE) != 0;
+}
+
+int dcache_status(void)
+{
+ return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
+}
diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c
new file mode 100644
index 00000000000..b83f1272c67
--- /dev/null
+++ b/arch/riscv/cpu/th1520/cpu.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Yao Zi <zi...@disroot.org>
+ *
+ * TH1520 SoC has a set of undocumented customized PMP registers that are
+ * configured through MMIO operation. It must be disabled before entering
+ * the DRAM region, or an exception will be raised.
+ */
+
+#include <asm/io.h>
+#include <cpu_func.h>
+
+#define TH1520_PMP_BASE (void *)0xffdc020000
+
+void th1520_invalidate_pmp(void)
+{
+ /* Invalidate the PMP configuration as in vendor U-Boot code */
+ writel(0x0, TH1520_PMP_BASE + 0x0);
+
+ invalidate_icache_all();
+}
diff --git a/arch/riscv/cpu/th1520/dram.c b/arch/riscv/cpu/th1520/dram.c
new file mode 100644
index 00000000000..91007c0a3d3
--- /dev/null
+++ b/arch/riscv/cpu/th1520/dram.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c
new file mode 100644
index 00000000000..aec398528d1
--- /dev/null
+++ b/arch/riscv/cpu/th1520/spl.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Yao Zi <zi...@disroot.org>
+ */
+#include <dm.h>
+#include <linux/sizes.h>
+#include <log.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_dram_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret) {
+ printf("failed to setup memory size and base: %d\n", ret);
+ return ret;
+ }
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/arch/riscv/include/asm/arch-th1520/cpu.h
b/arch/riscv/include/asm/arch-th1520/cpu.h
new file mode 100644
index 00000000000..837f0b8d06b
--- /dev/null
+++ b/arch/riscv/include/asm/arch-th1520/cpu.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2025 Yao Zi <zi...@disroot.org>
+ */
+
+#ifndef _ASM_TH1520_CPU_H_
+#define _ASM_TH1520_CPU_H_
+void th1520_invalidate_pmp(void);
+#endif /* _ASM_TH1520_CPU_H_ */
diff --git a/arch/riscv/include/asm/arch-th1520/spl.h
b/arch/riscv/include/asm/arch-th1520/spl.h
new file mode 100644
index 00000000000..59aed8cad62
--- /dev/null
+++ b/arch/riscv/include/asm/arch-th1520/spl.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Yao Zi <zi...@disroot.org>
+ */
+#ifndef _ASM_ARCH_TH1520_SPL_H_
+#define _ASM_ARCH_TH1520_SPL_H_
+
+void spl_dram_init(void);
+
+#endif // _ASM_ARCH_TH1520_SPL_H_
--
2.49.0
