Hi Sinan,
Thanks for your review.
Please see my comments.
Best Regards,
Yuan Yao
> -Original Message-
> From: Sinan Akman [mailto:si...@writeme.com]
> Sent: Saturday, August 15, 2015 12:28 AM
> To: Yuan Yao-B46683; Sun York-R58495; Wang Huan-B18965
> Cc: u-boot@lists.denx.de
> Subject: R
Hi york,
Is it for DDR4?
LS1021A doesn't use this file.
Best Regards,
Yuan Yao
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Friday, November 06, 2015 2:05 AM
> To: Yuan Yao-B46683
> Cc: Wang Huan-B18965 ; u-boot@lists.denx.de
> Subject: Re: [PATCH v2 4/5]
Thanks york,
So it seems I should moving the workaround out of DDR driver in "gen4" to SoC.
I think the workaround is not just only for ddr4.
And It should be as a workaround for the SOC.
From: York Sun
Sent: Tuesday, November 10, 2015 1:01
To: Yuan Yao-B
Hi York,
Thanks,
And is there any other comments for this set of patches?
Or could I send v3 for review?
Best Regards,
Yuan Yao
From: York Sun
Sent: Wednesday, November 11, 2015 0:43
To: Yuan Yao-B46683
Cc: Wang Huan-B18965; u-boot@lists.denx.de
Subject:
Hi Sinan Akman,
Thanks for your review.
There should not cause any problem with Rev1.0.
The workaround should also apply to rev1.0.
Best Regards,
Yuan Yao
> -Original Message-
> From: Sinan Akman [mailto:si...@writeme.com]
> Sent: Wednesday, November 25, 2015 12:10 AM
> To: Yuan Yao-B466
Hi Sinan Akman,
Thanks for your review, I will update my commit message in the next version.
Best Regards,
Yuan Yao
On 27/11/2015 12:04 AM, Sinan Akman wrote:
Hi Yuan
On 26/11/15 02:58 AM, Yuan Yao wrote:
> Both of the erratum:A008336 and A008514 are not apply to all the soc
> like:LS1021A
On 12/05/2015 01:12 AM, York Sun wrote:
> On 12/04/2015 01:37 AM, Yuan Yao wrote:
> > As the errata A008336 and A008514 do not apply to all LS series SoCs
> > (such as LS1021A, LS1043A) we move them to an soc specific file
> >
> > Signed-off-by: Yuan Yao
> > ---
> > Changed in v2:
> > Update t
Hi York,
I'm sorry I'm late replies.
Thanks for reminding me.
We have some investigates and then depend on the document we think both snoop
request and DVM are supported on those port.
So we think the setting should be ok in here.
Best Regards,
Yuan Yao
> -Original Message-
> From: Yor
Hi York,
Thanks for your review and modified.
Best Regards,
Yuan Yao
> -Original Message-
> From: Sun York-R58495
> Sent: Tuesday, December 15, 2015 9:00 AM
> To: Yuan Yao-B46683
> Cc: Wang Huan-B18965 ; u-boot@lists.denx.de
> Subject: Re: [PATCH 3/5] ls102xa: Enable snoop and DVM messa
Hi york,
The earlier SoC is just LS1021a rev1.0, but rev1.0 haven't delivery to the
customer.
Also the rev1.0 has since gone out of production.
So we don't have necessary to support rev1.0 because no one will or possibly to
use rev1.0.
Best Regards,
Yuan Yao
> -Original Message-
> From
Hi Sinan Akman,
Yes, I mean the Rev 1.0 silicon.
Sorry, I can't guarantee that there aren't any boards with Rev1.0 silicon are
in user's hands.
Because we have also delivery very little board with Rev1.0 silicon to
customer or developer for developing, assessing and verifying in the early
s
015 04:14 AM, Sinan Akman wrote:
> >
> >Hi Yuan
> >
> > On 19/10/15 05:21 AM, Yao Yuan wrote:
> >> Hi Sinan Akman,
> >>
> >> Yes, I mean the Rev 1.0 silicon.
> >> Sorry, I can't guarantee that there aren't any boards with Rev
Yes, it's an erratum. But I don't have the erratum number from the document. I
will connect the hardware team to check whether there is an erratum number.
Thanks.
Best Regards,
Yuan Yao
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 05,
On 06/22/2016 03:59 PM, Michael Trimarchi wrote:
> The S25FS128 is part of S25FS-S family physical sectors may be configured as a
> hybrid combination of eight 4-kB parameter sectors at the top or bottom of the
> address space with all but one of the remaining sectors being uniform size.
> This
>
On 06/22/2016 06:08 PM, Michael Trimarchi wrote:
> On Wed, Jun 22, 2016 at 10:00:49AM +0000, Yao Yuan wrote:
> > On 06/22/2016 03:59 PM, Michael Trimarchi wrote:
> > > The S25FS128 is part of S25FS-S family physical sectors may be
> > > configured as a hybrid combinat
On 03/03/2016 12:52 AM, York Sun wrote:
> On 03/02/2016 02:41 AM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > Signed-off-by: Yuan Yao
> > ---
> > include/configs/ls2080aqds.h | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/include/configs/ls2080aqds.h
> > b/include/configs/ls208
On 03/03/2016 12:52 AM, York Sun wrote:
> On 03/02/2016 02:41 AM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > If we want to access QSPI flash when boot from NAND,
>
> Is this "either this or that" choice? Is there any limitation after
> configuring pin
> mux?
No, there is no any limitation.
Just
On 03/03/2016 12:52 AM, York Sun wrote:
> On 03/02/2016 02:41 AM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > This patch is used for fix the bug below:
> > /***/
> > "Synchronous Abort" handler, esr 0x86000210
> > ELR: fff6cfb4
> > LR: fff6d3f0
> >
On 03/03/2016 12:52 AM, York Sun wrote:
> On 03/02/2016 02:41 AM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > This patch adds QSPI boot support for LS2080AQDS board.
> > The QSPI boot image need to be programmed into the QSPI flash first.
> > Then the booting will start from QSPI memory space.
> >
om; u-boot@lists.denx.de; Yunhui Cui
> > ; Yao Yuan
> > Subject: [PATCH 03/12] configs: ls2080aqds: Disable IFC NOR & QIXIS
> > when QSPI
> >
> > From: Yuan Yao
> >
> > When QSPI is enabled, NOR Flash and QIXIS can’t be accessed through
> > IFC du
om; u-boot@lists.denx.de; Yunhui Cui
> > ; Yao Yuan
> > Subject: [PATCH 12/12] LS2080QDS: QSPI boot: fix issues.
> >
> > From: Yuan Yao
> >
> > This patch is used for fix the bug below:
> > /***/
> > "Sync
om; u-boot@lists.denx.de; Yunhui Cui
> > ; Yao Yuan
> > Subject: [PATCH 02/12] configs: ls2080a_common: Remove duplicate NOR
> > configs
> >
> > From: Yuan Yao
> >
> > The NOR flash related configure options also appear in ls2080aqds.h
> > and ls2080ard
ariables, driver can't work correctly.
> > Converting the type of those variables to fdt_xxx_t.
> >
> > Signed-off-by: Yuan Yao
> > Signed-off-by: Prabhakar Kushwaha
> > Signed-off-by: Yuan Yao
> > ---
>
> Yuan,
>
> Did you mean to put both you
On 05/25 2016 AM, York Sun wrote:
> On 03/14/2016 11:44 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > There is the spansion S25FS-S family flash: s25fs256s1 on LS2080QDS
> > QSPI.
> >
> > Yuan Yao (5):
> > spi: fsl_qspi: Fix issues on arm64
> > spi: fsl_qspi: Assign AMBA mem according CS num
On 06/07/2016 02:41 AM, York Sun wrote:
> On 06/06/2016 03:53 AM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > This patch adds QSPI boot support for LS2080AQDS board.
> > The QSPI boot image need to be programmed into the QSPI flash first.
> > Then we can switch to booting from QSPI memory space.
>
On 06/08/2016 01:24 AM, York Sun wrote:
> On 06/07/2016 01:26 AM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > When QSPI is enabled, NOR flash and QIXIS can't be accessed through
> > IFC due to pin mux.
> >
> > Signed-off-by: Yuan Yao
> > ---
> > include/configs/ls2080aqds.h | 10 ++
> > 1
On 10/11/2016 11:04 PM, york sun wrote:
> On 10/10/2016 11:04 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > Signed-off-by: Yuan Yao
> > ---
> > board/freescale/ls2080aqds/README | 35
> > +++
> > 1 file changed, 35 insertions(+)
> >
> > diff --git a/board/freesca
On 10/12/2016 08:00 PM, York Sun wrote:
> On 10/11/2016 08:00 PM, Yao Yuan wrote:
> >>
> >> Yuan Yao,
> >>
> >> I think the procedure can be applied to many of our boards with QSPI,
> >> right? It may be better to move this information out of ls20
On 10/14/2016 11:36 PM, York Sun wrote:
> On 10/13/2016 11:45 PM, Yao Yuan wrote:
> > On 10/12/2016 08:00 PM, York Sun wrote:
> >> On 10/11/2016 08:00 PM, Yao Yuan wrote:
> >>>>
> >>>> Yuan Yao,
> >>>>
> >>>> I think
On Wed, Oct 26, 2016 at 3:39 PM, Jagan Teki wrote:
> On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > The QSPI support the direct 4bytes address command for flash
> > read/write/erase.
> > And the address can cover the whole QSPI memory space.
> >
> > Signed-off-by: Yua
On 03/04/2016 12:49 AM, York Sun wrote:
> On 03/02/2016 06:30 PM, Yao Yuan wrote:
> > On 03/03/2016 12:52 AM, York Sun wrote:
> >> On 03/02/2016 02:41 AM, Yuan Yao wrote:
> >>> From: Yuan Yao
> >>>
> >>> This patch adds QSPI boot support for
On 03/23/2016 03:09 AM, York Sun wrote:
> On 03/06/2016 11:56 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > This series add support for QSPI boot on LS2080AQDS.
> >
> > Yuan Yao (11):
> > armv8: ls2080aqds: Select QSPI CLK div via SCFG
> > configs: ls2080a_common: Remove duplicate NOR configs
On 01/25/2016 04:16 AM, York Sun wrote:
> On 01/22/2016 07:43 AM, Scott Wood wrote:
> > On 01/21/2016 09:35 PM, Qianyu Gong wrote:
> >>
> >>> -Original Message-
> >>> From: Scott Wood
> >>> Sent: Friday, January 22, 2016 3:30 AM
> >>> To: Qianyu Gong ; u-boot@lists.denx.de;
> >>> r58...@fre
On Wed, Oct 26, 2016 at 3:39 PM, Jagan Teki wrote:
> On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > Some new flash don't support bar register but use 4bytes address to
> > support exceed 16MB flash size.
> > So add flash flag:
> > ADDR_4B
> > for some flash which supp
On 11/08/2016 12:46 PM, York Sun wrote:
> On 11/07/2016 07:58 PM, Yao Yuan wrote:
> > On 11/08/2016 02:27 AM, York Sun wrote:
> >> On 10/10/2016 11:09 PM, Yuan Yao wrote:
> >>> From: Yuan Yao
> >>>
> >>> Add the address value and size value
On 11/08/2016 02:27 AM, York Sun wrote:
> On 10/25/2016 07:10 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > The default configuration for QSPI AHB bus can't support 16MB+.
> > But some flash on NXP layerscape board are more than 16MB.
>
> So what do you do?
>
> Is this an erratum workaround? If
On 11/08/2016 02:17 PM, York Sun wrote:
> On 10/16/2016 08:58 PM, Yao Yuan wrote:
> > Hi York,
> >
> > It seems arch/arm/cpu/armv8/fsl-layerscape/doc/README.* is better.
> > I will update my patch and resend soon.
> >
>
> Did you send the update? BTW, I thi
On 11/08/2016 02:27 AM, York Sun wrote:
> On 10/10/2016 11:09 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > Add the address value and size value name for QSPI dts node.
>
> This message doesn't match the change. Do you call "QuadSPI" the address
> value name?
>
Yes, I always call QuadSPI as QS
On 11/08/2016 12:46 PM, York Sun wrote:
> On 11/07/2016 07:52 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > Signed-off-by: Yuan Yao
> > ---
> > Changed in v2:
> > Move the readme for QSPI deploy out of only for ls2080aqds.
> > ---
> > .../arm/cpu/armv8/fsl-layerscape/doc/README.deploy | 44
On 11/09/2016 02:10 AM, York Sun wrote:
> On 11/07/2016 09:44 PM, Yao Yuan wrote:
> > On 11/08/2016 12:46 PM, York Sun wrote:
> >> On 11/07/2016 07:52 PM, Yuan Yao wrote:
> >>> From: Yuan Yao
> >>>
> >>> Signed-off-by: Yuan Yao
> >
On 11/15/2016 01:47 AM, York Sun wrote:
> On 11/07/2016 10:03 PM, Yao Yuan wrote:
> > On 11/08/2016 02:27 AM, York Sun wrote:
> >> On 10/25/2016 07:10 PM, Yuan Yao wrote:
> >>> From: Yuan Yao
> >>>
> >>> The default configuration for QSPI AH
On Wed, Oct 26, 2016 at 4:39 PM, Jagan Teki wrote:
> On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > Some new flash don't support bar register but use 4bytes address to
> > support exceed 16MB flash size.
> > So add flash flag:
> > ADDR_4B
> > for some flash which sup
On 11/15/2016 02:27 AM, York Sun wrote:
> On 11/07/2016 10:03 PM, Yao Yuan wrote:
> > On 11/08/2016 02:27 AM, York Sun wrote:
> >> On 10/25/2016 07:10 PM, Yuan Yao wrote:
> >>> From: Yuan Yao
> >>>
> >>> The default configuration for QSPI AH
On 12/01/2016 07:33 PM, York Sun wrote:
> On 11/29/2016 07:33 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > The default configuration for QSPI AHB bus can't support 16MB+.
> > But some flash on NXP layerscape board are more than 16MB.
> >
> > Signed-off-by: Yuan Yao
> > ---
> > Changed in v2:
>
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