On 03/03/2016 10:58AM, Prabhakar Kushwaha wrote: > > -----Original Message----- > > From: Yuan Yao [mailto:yao.y...@freescale.com] > > Sent: Wednesday, March 02, 2016 4:02 PM > > To: york sun <york....@nxp.com> > > Cc: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>; > > pratiyush.srivast...@freescale.com; u-boot@lists.denx.de; Yunhui Cui > > <yunhui....@nxp.com>; Yao Yuan <yao.y...@nxp.com> > > Subject: [PATCH 03/12] configs: ls2080aqds: Disable IFC NOR & QIXIS > > when QSPI > > > > From: Yuan Yao <yao.y...@nxp.com> > > > > When QSPI is enabled, NOR Flash and QIXIS can’t be accessed through > > IFC due to pin muxing. > > > > Enable QIXIS accessing through I2C. > > > > Signed-off-by: Yuan Yao <yao.y...@nxp.com> > > --- > > include/configs/ls2080aqds.h | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/include/configs/ls2080aqds.h > > b/include/configs/ls2080aqds.h index dab3820..3edb0b9 100644 > > --- a/include/configs/ls2080aqds.h > > +++ b/include/configs/ls2080aqds.h > > @@ -17,8 +17,18 @@ unsigned long get_board_ddr_clk(void); #endif > > > > #define CONFIG_SYS_FSL_CLK > > + > > +#ifdef CONFIG_FSL_QSPI > > +#define CONFIG_SYS_NO_FLASH > > +#undef CONFIG_CMD_IMLS > > +#define CONFIG_SYS_CLK_FREQ 100000000 > > +#define CONFIG_DDR_CLK_FREQ 133333333 > > +#define CONFIG_QIXIS_I2C_ACCESS > > If we are accessing QIXIS via I2c then why hard-coding SYSCLK and DDRCLK? >
If we aren't hard-coding SYSCLK and DDRCLK. We don't have any other way to get the SYSCLK and DDRCLK. We can't get it by read FPGA before config I2C. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
