Since mt7620 is added into Kconfig, the CONFIG_SOC_MT7628=y which is
omitted by default must be added back, otherwise make xxx_defconfig for
these boards will be configured for mt7620 platform.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
The mt7620_rfb board supports integrated 10/100M PHYs plus two external
giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.
The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
16MB SPI-NOR flash.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes
registers (DLL and DLM).
The driver supports of-platdata which is useful for tiny SPL.
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: replace non-DM code with of-platdata
---
drivers/serial/Kconfig | 20 +++
drivers/serial/Makefile| 1
This patch adds pinctrl support for MediaTek MT7620 SoC.
The MT7620 SoC supports only pinmux.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
drivers/pinctrl/mtmips/Kconfig | 9 ++
drivers/pinctrl/mtmips/Makefile | 1 +
drivers/pinctrl/mtmips/pinctrl
This patch adds reset controller bits definition header file for MediaTek
MT7620 SoC
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
include/dt-bindings/reset/mt7620-reset.h | 35
1 file changed, 35 insertions(+)
create mode 100644 include/dt
This patch adds GPIO controller driver for MediaTek MT7620 SoC
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/mt7620_gpio.c | 146
register groups cannot operates simulataneously so
they are implemented as one controller.
Signed-off-by: Weijie Gao
---
v3 changes: use bool instead of int in for mt7620_spi_set_cs()
v2 changes: none
---
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mt7620_spi.c
This patch adds watchdog support for the Mediatek MT7620 SoC
Reviewed-by: Jagan Teki
Signed-off-by: Weijie Gao
---
v3 changes: add detail comments for mt7620_wdt_expire_now()
v2 changes: add expire_now
---
drivers/watchdog/Kconfig | 7 ++
drivers/watchdog/Makefile | 1 +
drivers
This patch adds a clock driver for MediaTek MT7620 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
drivers/clk/mtmips/Makefile| 1 +
drivers
This patch adds USB PHY driver for MediaTek MT7620 SoC
Signed-off-by: Weijie Gao
---
v3 changes: remove duplicated dev field in mt7620_usb_phy
v2 changes: none
---
drivers/phy/Kconfig | 7 +++
drivers/phy/Makefile | 1 +
drivers/phy/mt7620-usb-phy.c | 110
The driver is missing pad control settings (pad delay and pad conf) for
the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
encounter CRC error on data transfers.
This patch adds default pad control settings for mt7620_compat.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2
the intergrited FE PHY, or the xMII.
Port 5 always connects to the xMII. Port 6 is the CPU port.
This driver supports MT7530 giga switch connects to port 5.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
drivers/net/Kconfig | 12 +
drivers/net/Makefile |1
It turns out that the sclk cycles used by mt7620/mt7628 is the same as
other chips (20 bits, 1048576), not 65536.
This patch removes sclk_cycle_shift from dev_comp, and uses a macro with
a value 20 instead.
Signed-off-by: Weijie Gao
---
v3 changes: new
---
drivers/mmc/mtk-sd.c | 13
Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can
be probed before relocation even if u-boot,dm-pre-reloc is not present
in the dts.
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: new
---
drivers/reset/reset-mtmips.c | 1 +
1 file changed, 1 insertion(+)
diff
Update maintainer for MediaTek MIPS platform
Acked-by: Stefan Roese
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v3 changes: none
v2 changes: none
---
MAINTAINERS | 23 +++
1 file changed, 23 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 874cf2c0e5
Currently this driver does not set the value of plat->cfg.f_max, which
results in that MMC framework will always run at the lowest frequency.
This patch sets plat->cfg.f_max to the maximum allowed frequency, which is
half of the source clock frequency.
Signed-off-by: Weijie Gao
---
v3 c
On Mon, 2020-11-09 at 09:51 +0100, Stefan Roese wrote:
> On 09.11.20 09:25, Weijie Gao wrote:
> > This patch adds reset controller bits definition header file for MediaTek
> > MT7620 SoC
> >
> > Signed-off-by: Weijie Gao
>
> Just curious: Where are you includ
On Mon, 2020-11-09 at 10:00 +0100, Stefan Roese wrote:
> On 09.11.20 09:28, Weijie Gao wrote:
> > The driver is missing pad control settings (pad delay and pad conf) for
> > the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
> > encounter CRC er
ected.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: none
---
arch/mips/dts/Makefile | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index dc85901dca..e82f96d4e4 100644
--- a
nstead
- Fix dev_err related compilation error
- Add expire_now for mt7620-wdt
- Remove use of common.h
Weijie Gao (23):
mips: dts: switch to board defines for dtb for mtmips
mips: mtmips: move mt7628 related Kconfig into mt7628 subdirectory
mips: mtmips: select SYSRESET for mt7628 only
mips:
This patch is a preparation for add a new soc fot mtmips.
Move all mt7628 related Kconfig (boards and UART selection) into mt7628
subdirectory and make sure the top directory of mtmips contains only
selection for SoCs.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3
Currently only mt7628 needs the sysreset driver, do not select it for
mt7620.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: new
---
arch/mips/Kconfig | 1 -
arch/mips/mach-mtmips/Kconfig | 1 +
2 files changed, 1 insertion
The sysreset driver has a config CONFIG_SPL_SYSRESET for the spl stage.
Change CONFIG_SYSRESET to CONFIG_IS_ENABLED(SYSRESET) will give spl a
chance to use _machine_restart instead of the sysreset driver.
Reviewed-by: Stefan Roese
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v4
This patch adds support for mtmips SoCs to initialize the SDRAM.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: none
---
arch/mips/mach-mtmips/ddr_init.c | 59
arch/mips/mach-mtmips/include/mach/ddr.h | 4
CONFIG_SYS_SDRAM_BASE points to cached memory, i.e. KSEG0, which is not
suitable for detecting memory size.
Replace CONFIG_SYS_SDRAM_BASE with KSEG1, and make dram_init() always do
memory size detection in any stage.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3
The mt7620_rfb board supports integrated 10/100M PHYs plus two external
giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.
The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
16MB SPI-NOR flash.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
Since mt7620 is added into Kconfig, the CONFIG_SOC_MT7628=y which is
omitted by default must be added back, otherwise make xxx_defconfig for
these boards will be configured for mt7620 platform.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes
This patch adds support for MediaTek MT7620 SoC.
All files are dedicated for u-boot.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: remove use of common.h
---
arch/mips/dts/mt7620-u-boot.dtsi | 14 +
arch/mips/dts/mt7620.dtsi
registers (DLL and DLM).
The driver supports of-platdata which is useful for tiny SPL.
Reviewed-by: Stefan Roese
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v4 changes: remove unused non-DM code in drivers/serial/serial.c
v3 changes: none
v2 changes: replace non-DM code with of-platdata
This patch adds reset controller bits definition header file for MediaTek
MT7620 SoC
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: none
---
include/dt-bindings/reset/mt7620-reset.h | 35
1 file changed, 35
This patch adds watchdog support for the Mediatek MT7620 SoC
Reviewed-by: Stefan Roese
Reviewed-by: Jagan Teki
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: add detail comments for mt7620_wdt_expire_now()
v2 changes: add expire_now
---
drivers/watchdog/Kconfig | 7
This patch adds a clock driver for MediaTek MT7620 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: none
---
drivers/clk
This patch adds GPIO controller driver for MediaTek MT7620 SoC
Reviewed-by: Stefan Roese
Reviewed-by: Simon Glass
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: none
---
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio
This patch adds pinctrl support for MediaTek MT7620 SoC.
The MT7620 SoC supports only pinmux.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: none
---
drivers/pinctrl/mtmips/Kconfig | 9 ++
drivers/pinctrl/mtmips/Makefile
register groups cannot operates simulataneously so
they are implemented as one controller.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: use bool instead of int in for mt7620_spi_set_cs()
v2 changes: none
---
drivers/spi/Kconfig | 7 +
drivers/spi
the intergrited FE PHY, or the xMII.
Port 5 always connects to the xMII. Port 6 is the CPU port.
This driver supports MT7530 giga switch connects to port 5.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: none
---
drivers/net/Kconfig
off-by: Weijie Gao
---
v4 changes: change plat->cfg.f_max to equal to host->src_clk_freq
v3 changes: new
---
drivers/mmc/mtk-sd.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index f4ff8822f2..77fda0eab0 100644
--- a/drivers/mmc/mtk-sd.c
+++ b
The driver is missing pad control settings (pad delay and pad conf) for
the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
encounter CRC error on data transfers.
This patch adds default pad control settings for mt7620_compat.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
This patch adds USB PHY driver for MediaTek MT7620 SoC
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: remove duplicated dev field in mt7620_usb_phy
v2 changes: none
---
drivers/phy/Kconfig | 7 +++
drivers/phy/Makefile | 1 +
drivers
Update maintainer for MediaTek MIPS platform
Acked-by: Stefan Roese
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: none
---
MAINTAINERS | 23 +++
1 file changed, 23 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
It turns out that the sclk cycles used by mt7620/mt7628 is the same as
other chips (20 bits, 1048576), not 65536.
This patch removes sclk_cycle_shift from dev_comp, and uses a macro with
a value 20 instead.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes
Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can
be probed before relocation even if u-boot,dm-pre-reloc is not present
in the dts.
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v4 changes: none
v3 changes: none
v2 changes: new
---
drivers/reset/reset-mtmips.c
On Sun, 2021-11-21 at 21:14 +0200, Ramon Fried wrote:
> On Fri, Nov 19, 2021 at 3:37 AM Weijie Gao
> wrote:
> >
> > This patch adds GMAC support for MediaTek MT7621 SoC.
> > MT7621 has the same GMAC/Switch configuration as MT7623.
> >
> > Signed-off-by: Weij
On Fri, 2021-11-26 at 12:44 -0500, Sean Anderson wrote:
> On 11/18/21 8:35 PM, Weijie Gao wrote:
> > This patch adds a clock driver for MediaTek MT7621 SoC.
> > This driver provides clock gate control as well as getting clock
> > frequency
> > for CPU/SYS/XTAL and some p
tstc() again after
the 10ms timeout.
This patch fixes this issue by letting bootmenu_loop check tstc()
twice.
Signed-off-by: Weijie Gao
---
common/menu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/common/menu.c b/common/menu.c
index 8cc9bf06d9c..48ab7f0f398 100644
tstc() again after
the 10ms timeout.
This patch fixes this issue by letting bootmenu_loop check tstc()
twice.
Signed-off-by: Weijie Gao
---
common/menu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/common/menu.c b/common/menu.c
index 5fd705039fc..bd2ac3e0ed9 1006
Record the last active menu item and check if it equals to the
current selected item before reprint.
Signed-off-by: Weijie Gao
---
cmd/bootmenu.c | 16 +++-
include/menu.h | 1 +
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index
input data.
Signed-off-by: Weijie Gao
---
boot/pxe_utils.c | 2 +-
cmd/bootmenu.c | 2 +-
cmd/eficonfig.c | 2 +-
common/menu.c| 11 +++
include/menu.h | 1 +
5 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index d6a4b2cb859
tstc() again after
the 10ms timeout.
This patch fixes this issue by letting bootmenu_loop check tstc()
twice.
Tested-By: E Shattow
Signed-off-by: Weijie Gao
---
common/menu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/common/menu.c b/common/menu.c
index 8cc9bf06d9c.
Hi Daniel,
On Sat, 2024-10-26 at 20:23 +0100, Daniel Golle wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Hi!
>
> On Mon, Oct 21, 2024 at 08:56:42AM +0800, Weijie Gao wrote:
> > It
On Mon, 2024-10-28 at 03:33 +0100, Marek Vasut wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> On 10/28/24 1:25 AM, Weijie Gao wrote:
> > Hi Daniel,
> >
> > On Sat, 2024-10-26 a
Hi Daniel,
On Thu, 2024-10-31 at 19:16 +, Daniel Golle wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> On Tue, Oct 29, 2024 at 05:47:10PM +0800, Weijie Gao wrote:
> > It's obser
uot;, "iocfg_tr", "iocfg_br",
> + "iocfg_rb", "iocfg_lb", "iocfg_tl",
> "eint";
> gpio: gpio-controller {
> gpio-controller;
> --
> 2.47.1
>
Thanks!
Reviewed-by: Weijie Gao
Tested-by: Weijie Gao
7531";
> - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
>
> fixed-link {
> speed = <2500>;
> @@ -56,7 +56,7 @@
> };
> };
>
> -&pinctrl {
> +&pio {
> spi_flash_pins: spi0-pins-func-1 {
> mux {
> function = "flash";
> diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-
> sd-rfb.dts
> index ec80a2fb710..e5fb4d73e70 100644
> --- a/arch/arm/dts/mt7986b-sd-rfb.dts
> +++ b/arch/arm/dts/mt7986b-sd-rfb.dts
> @@ -49,7 +49,7 @@
> mediatek,gmac-id = <0>;
> phy-mode = "2500base-x";
> mediatek,switch = "mt7531";
> - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
>
> fixed-link {
> speed = <2500>;
> @@ -57,7 +57,7 @@
> };
> };
>
> -&pinctrl {
> +&pio {
> spi_flash_pins: spi0-pins-func-1 {
> mux {
> function = "flash";
> --
> 2.47.1
>
Thanks!
Reviewed-by: Weijie Gao
Tested-by: Weijie Gao
;
> static const char *const mt7981_pinctrl_register_base_names[] = {
> - "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
> "iocfg_rb_base",
> - "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base",
> "iocfg_tl_base",
> + "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
> + "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
> + "eint",
> };
>
> static const struct mtk_pinctrl_soc mt7981_data = {
> --
> 2.47.1
>
Thanks!
Reviewed-by: Weijie Gao
Tested-by: Weijie Gao
";
> + reg-names = "gpio", "iocfg_rt", "iocfg_rb",
> + "iocfg_lt", "iocfg_lb", "iocfg_tr",
> + "iocfg_tl", "eint";
> gpio: gpio-controller {
> gpio-controller;
> #gpio-cells = <2>;
> --
> 2.47.1
>
>
Thanks!
Reviewed-by: Weijie Gao
Tested-by: Weijie Gao
reg = <0x11e1 0x700>;
> + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@11e10700 {
> + reg = <0x11e10700 0x900>;
> + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + mediatek,syscon-type = <&topmisc 0x218 0>;
> + status = "okay";
> + };
> + };
> };
> --
> 2.47.1
>
Thanks!
Reviewed-by: Weijie Gao
Tested-by: Weijie Gao
;,
> + <0 0 0 3 &pcie_intc 2>,
> + <0 0 0 4 &pcie_intc 3>;
> +
> + status = "disabled";
> +
> + pcie_intc: interrupt-controller {
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + };
> + };
> +
> usbtphy: usb-phy@11e1 {
> compatible = "mediatek,mt7981",
> "mediatek,generic-tphy-v2";
> --
> 2.47.1
>
Thanks!
Reviewed-by: Weijie Gao
Tested-by: Weijie Gao
This patch enables switch auto-detction for mt7981 as some new mt7981
boards will use AN8855 ethernet switch.
Signed-off-by: Weijie Gao
---
arch/arm/dts/mt7981-emmc-rfb.dts | 2 +-
arch/arm/dts/mt7981-rfb.dts | 2 +-
arch/arm/dts/mt7981-sd-rfb.dts | 2 +-
3 files changed, 3 insertions
This patch add support to read register base address by name if
provided.
Also devfdt_get_addr_* is changed to dev_read_addr_* to support DT
live tree.
Signed-off-by: Weijie Gao
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
The change from pinctrl to pio was missing in mt7986-u-boot.dtsi ans will
cause build failure. Now fix it.
Fixes: f1775996ba9 (mediatek: mt7986: move gpio-controller up and rename
pinctrl to pio)
Signed-off-by: Weijie Gao
---
arch/arm/dts/mt7986-u-boot.dtsi | 2 +-
1 file changed, 1 insertion
Hi Mauri,
Here's an example:
https://github.com/openwrt/openwrt/blob/main/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch#L316
Weijie
Mauri Sandberg 于2025年2月8日周六 03:06写道:
>
> Hello all,
>
> I have a MT7621A basec SoC, which I am trying to update the boot pr
This patch add support to read register base address by name if
provided.
Also devfdt_get_addr_* is changed to dev_read_addr_* to support DT
live tree.
Signed-off-by: Weijie Gao
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
The reg-names in mt7988.dtsi have no _base suffix. Remove the suffix
will also make it match upstream linux format.
Fixes: 8c2cb748ef5 (pinctrl: mediatek: mt7988: rename reg-names to upstream
linux format)
Signed-off-by: Weijie Gao
---
drivers/pinctrl/mediatek/pinctrl-mt7988.c | 3 +--
1 file
The change from pinctrl to pio was missing in mt7986-u-boot.dtsi and will
cause build failure. Now fix it.
Fixes: f1775996ba9 (mediatek: mt7986: move gpio-controller up and rename
pinctrl to pio)
Signed-off-by: Weijie Gao
---
arch/arm/dts/mt7986-u-boot.dtsi | 2 +-
1 file changed, 1 insertion
According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL
shares the same parent selection with CLK_TOP_IRRX_SEL, while the
present parent selection for CLK_TOP_F10M_REF_SEL is actually used
for CLK_TOP_SGMII_REF_1_SEL.
Signed-off-by: Weijie Gao
---
drivers/clk/mediatek/clk-mt7629.c
Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow
sgmiisys1 work correctly.
Signed-off-by: Weijie Gao
---
arch/arm/dts/mt7629.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index 7dea7809c70
Enable GDMA cpu bridge only when 10Gb interface is enabled for GMAC other
than GMAC0, or when MT7988 internal switch is used.
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/mtk_eth.c b/drivers/net
Not all platforms supports sgmii and/or usxgmii. So we add Kconfig
options for these features and enable them only for supported
platforms.
Signed-off-by: Weijie Gao
---
drivers/net/Kconfig | 12
drivers/net/mtk_eth.c | 39 +--
2 files changed
.
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth.c | 10 --
drivers/net/mtk_eth.h | 8 ++--
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index b8cb1f64995..592764df3d1 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net
This patch adds support for 10GBASE-R interface mode
Signed-off-by: Bo-Cun Chen
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth.c | 83 +--
1 file changed, 81 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
MT7629 need extra setting for gmac2 to work. So additional
capability is added for mt7629 to handle this case.
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth.c | 6 ++
drivers/net/mtk_eth.h | 7 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/net/mtk_eth.c b/drivers/net
The SYSCFG0 should be SYSCFG1 according to the programming guide.
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth.c | 14 +++---
drivers/net/mtk_eth.h | 12 ++--
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
The register field for SGMII speed selection is a 2-bit field with
value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
So it's necessary to set both bits instead of just setting/clearing
only the lower bit.
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth.c | 12 ++--
driver
This patch series contains fixes and updates for mtk_eth driver.
Weijie Gao (10):
clk: mediatek: mt7629: fix parent clock of some top clock muxes
arm: dts: mt7629: fix sgmii clock selection for ethernet
net: mediatek: use correct register field for SGMII speed selection
net: mediatek
The wget command currently cannot work correctly with mtk_eth driver.
This patch fixed this by increase DMA ring size and invalidate ring data
after use.
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/net
cular board, Kconfig
options are added to allow user to select which switch should be
built into u-boot. If multiple switches are selected, auto-detecting
can also be enabled.
Signed-off-by: Weijie Gao
---
drivers/net/Kconfig | 21 +-
drivers/net/Makefile| 2 +-
dr
Airoha AN8855 is a 5-port gigabit switch with a 2.5G HSGMII CPU port
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth/Kconfig |4 +
drivers/net/mtk_eth/Makefile |1 +
drivers/net/mtk_eth/an8855.c | 1096 ++
3 files changed, 1101 insertions(+)
create
This patch adds support for MediaTek MT7987.
MT7987 features MediaTek NETSYS v3, similar to MT7988, features three GMACs
which support 2.5Gb HSGMII. One 2.5Gb PHY is also embedded an can be
connected to a dedicated GMAC.
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth/Kconfig | 4
This patch series will split the switch initialization code from mtk_eth
driver into their own files and then add new SoC and switch support.
Weijie Gao (3):
net: mediatek: split ethernet switch code from mtk_eth.c
net: mediatek: add support for MediaTek MT7987 SoC
net: mediatek: add
This patch adds clock driver support for MediaTek MT7987 SoC
Signed-off-by: Sam Shih
Signed-off-by: Weijie Gao
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt7987.c | 848 ++
.../dt-bindings/clock/mediatek,mt7987-clk.h | 206
This patch series add support for MediaTek MT7987 SoC with its reference
boards and related drivers.
This patch series add basic boot support on eMMC/SD/SPI-NOR/SPI-NAND for these
boards. The clock, pinctrl drivers and the SoC initializaton code are also
included.
Weijie Gao (5):
clk: mediatek
This patch adds pinctrl and gpio support for MT7987 SoC
Signed-off-by: Weijie Gao
---
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt7987.c | 736 ++
3 files changed, 741 insertions
This patch adds eMMC/SD support for MT7987 SoC
Signed-off-by: Weijie Gao
---
drivers/mmc/mtk-sd.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index d676cf9e314..2bc700b0d05 100644
--- a/drivers/mmc/mtk
x kernel, and OF_UPSTREAM will also be switched on.
Signed-off-by: Weijie Gao
---
arch/arm/dts/mt7987-emmc.dtsi | 50 ++
arch/arm/dts/mt7987-netsys-u-boot.dtsi| 51 ++
arch/arm/dts/mt7987-pinctrl-u-boot.dtsi | 146
arch/arm/dts/mt7987-pinctrl.dtsi
(spi0)
2. mt7987_emmc_rfb_defconfig - eMMC + SPI-NOR (spi2)
3. mt7987_sd_rfb_defconfig - SD + SPI-NOR (spi2)
Note: spi2 also supports booting from SPI-NAND, but not the default option.
Signed-off-by: Sam Shih
Signed-off-by: Weijie Gao
---
arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi | 61
Update mt7981 pinctrl driver based on upstream kernel
Signed-off-by: Sam Shih
Signed-off-by: Weijie Gao
---
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 51 ---
1 file changed, 45 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
b
This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises
Signed-off-by: Weijie Gao
---
drivers/net/mtk_eth/an8855.
nit
Since initr_net() hasn't be called, iterating over the mii_devs
will access to physical address 0 (mii_devs.next == NULL) and will
cause the crash.
The fix is to define mii_devs using:
> static LIST_HEAD(mii_devs);
As the "current_mii" is defined as a static variable, it will
: Weijie Gao
---
Changes in v2:
* Remove mt7629-rfb.dtb from arch/arm/dts/Makefile
* Add wdt-reboot node to make reset command work
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/mt7629-rfb-u-boot.dtsi| 119 +++-
arch/arm/dts/mt7629-rfb.dts| 123 -
arch
This patch series migrates MediaTek MT7629 to OF_UPSTREAM
Changes in v2:
* Remove mt7629-rfb.dtb from arch/arm/dts/Makefile
* Add wdt-reboot node to make reset command work
Sam Shih (2):
clk: mediatek: mt7629: fix gate offset of peri clock tree
board: mediatek: mt7629: Migrate to OF_UPSTREAM
clock
from <&pericfg>.
Since CLK_PERIBUS_SEL clock is not required in U-Boot, add a clock gate
offset for the pericfg clock tree to resolve this problem.
Signed-off-by: Sam Shih
Signed-off-by: Weijie Gao
---
drivers/clk/mediatek/clk-mt7629.c | 14 +-
1 file changed, 13 insert
: Weijie Gao
---
arch/arm/dts/mt7629-rfb-u-boot.dtsi| 113 +++-
arch/arm/dts/mt7629-rfb.dts| 123 -
arch/arm/dts/mt7629.dtsi | 360 -
configs/mt7629_rfb_defconfig | 3 +-
include/dt-bindings/clock/mt7629-clk.h | 206
clock
from <&pericfg>.
Since CLK_PERIBUS_SEL clock is not required in U-Boot, add a clock gate
offset for the pericfg clock tree to resolve this problem.
Signed-off-by: Sam Shih
Signed-off-by: Weijie Gao
---
drivers/clk/mediatek/clk-mt7629.c | 14 +-
1 file changed, 13 insert
This patch series migrates MediaTek MT7629 to OF_UPSTREAM
Sam Shih (2):
clk: mediatek: mt7629: fix gate offset of peri clock tree
board: mediatek: mt7629: Migrate to OF_UPSTREAM
arch/arm/dts/mt7629-rfb-u-boot.dtsi| 113 +++-
arch/arm/dts/mt7629-rfb.dts| 123 -
arc
The function board_late_init defined for mt7622 is useless now. Just
remove it.
Signed-off-by: Weijie Gao
---
board/mediatek/mt7622/mt7622_rfb.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/board/mediatek/mt7622/mt7622_rfb.c
b/board/mediatek/mt7622/mt7622_rfb.c
index e7f492a13bc
This patch adds missing initialization of fields in INFRA_MUX struct
which caused uart broken after any other infra mux being enabled by
'clk_prepare_enable'
Signed-off-by: Sam Shih
Signed-off-by: Weijie Gao
---
drivers/clk/mediatek/clk-mt7981.c | 1 +
drivers/clk/mediatek/clk-mt
This patch series contains fixes and updates for MediaTek platform,
including drivers, board and arch files.
Weijie Gao (15):
board: mediatek: mt7622: remove board_late_init
clk: mediatek: fix uninitialized fields issue in INFRA_MUX struct
configs: mt7629: move image load address to
Update the image load address to ensure it matches the mt7629 NOR
controller's DMA alignment requirements.
Signed-off-by: Sam Shih
Signed-off-by: Weijie Gao
---
configs/mt7629_rfb_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/mt7629_rfb_defcon
This patch sets mt7988 image load address to 0x4400 to support loading
larger images.
Signed-off-by: Weijie Gao
---
configs/mt7988_rfb_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig
index 4d7454d5d39
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