revision and select the fitting RAM settings.
Teresa
Teresa Remmet (6):
board: phytec: Add common PHYTEC SoM detection
board: phytec: common: Add imx8m specific EEPROM detection support
board: phytec: phycore-imx8mp: Add EEPROM detection initialisation
board: phytec: phycore_imx8mp: Update 2GB
Recent shipped PHYTEC SoMs come with an i2c EEPROM containing
information about the hardware such as board revision and variant.
This can be used for RAM detection and loading device tree overlays
during kernel start.
Signed-off-by: Teresa Remmet
---
board/phytec/common/Kconfig
Add imx8m specific detection part. Which includes checking the
EEPROM data for article number options.
Signed-off-by: Teresa Remmet
---
board/phytec/common/Kconfig | 8 +
board/phytec/common/Makefile | 1 +
board/phytec/common/imx8m_som_detection.c | 169
Add EEPROM detection initialisation for phyCORE-i.MX8MM and
print SoM information during boot when successful.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/Kconfig | 1 +
board/phytec/phycore_imx8mp/spl.c | 19 +++
configs/phycore-imx8mp_defconfig| 1 +
3
Due to PCB layout constraints in PCB revisions until including 1549.2,
a RAM frequency of 2 GHz can cause rare instabilities. Set the RAM
frequency to 1.5 GHz to achieve a stable system under all conditions.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/lpddr4_timing.c | 278
Add helper function to read out the PCB revision of a PHYTEC SoM.
Signed-off-by: Teresa Remmet
---
board/phytec/common/phytec_som_detection.c | 15 +++
board/phytec/common/phytec_som_detection.h | 5 +
2 files changed, 20 insertions(+)
diff --git a/board/phytec/common
Starting with PCB revision 3 we can safely make use of higher RAM
frequency again. Make use of the EEPROM detection to determine the
revision and use the updated RAM timings for new SoMs.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/spl.c | 61 +++
1
Hello Yannic,
Am Freitag, dem 28.07.2023 um 15:08 +0200 schrieb Yannic Moog:
> Hi Teresa,
>
> On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
> > Add imx8m specific detection part. Which includes checking the
> > EEPROM data for article number options.
> >
Hello Yannic,
Am Donnerstag, dem 03.08.2023 um 10:10 +0200 schrieb Yannic Moog:
> Hello Teresa,
>
> On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
> > Add EEPROM detection initialisation for phyCORE-i.MX8MM and
> > print SoM information during boot when successful
Hello Yannic,
Am Dienstag, dem 08.08.2023 um 09:25 +0200 schrieb Yannic Moog:
> Hello Teresa,
>
> On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
> > Due to PCB layout constraints in PCB revisions until including
> > 1549.2,
> > a RAM frequency of 2 GHz can ca
Hello Yannic,
Am Donnerstag, dem 03.08.2023 um 11:09 +0200 schrieb Yannic Moog:
> Hello Teresa,
>
> On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
> > Starting with PCB revision 3 we can safely make use of higher RAM
> > frequency again. Make use of the EEPROM detec
detect the
PCB revision and select the fitting RAM settings.
Changes in v2:
- fix wrong RAM Timing values as pointed out by Yannic
- removed superfluous goto
- removed blank line at EOF
- fix string conversion to integer
- fix typo s/revsions/revisions
Teresa
Teresa Remmet (6):
board: phytec: Add
Recent shipped PHYTEC SoMs come with an i2c EEPROM containing
information about the hardware such as board revision and variant.
This can be used for RAM detection and loading device tree overlays
during kernel start.
Signed-off-by: Teresa Remmet
---
Changes in v2:
- none
---
board/phytec
Add imx8m specific detection part. Which includes checking the
EEPROM data for article number options.
Signed-off-by: Teresa Remmet
---
Changes in v2:
- remove blank line at EOF
- fix string conversion to integer
- fix typo s/revsions/revisions
---
board/phytec/common/Kconfig
Add EEPROM detection initialisation for phyCORE-i.MX8MM and
print SoM information during boot when successful.
Signed-off-by: Teresa Remmet
---
Changes in v2:
- removed superfluous goto
---
board/phytec/phycore_imx8mp/Kconfig | 1 +
board/phytec/phycore_imx8mp/spl.c | 17
Due to PCB layout constraints in PCB revisions until including 1549.2,
a RAM frequency of 2 GHz can cause rare instabilities. Set the RAM
frequency to 1.5 GHz to achieve a stable system under all conditions.
Signed-off-by: Teresa Remmet
---
Changes in v2:
- none
---
board/phytec/phycore_imx8mp
Starting with PCB revision 3 we can safely make use of higher RAM
frequency again. Make use of the EEPROM detection to determine the
revision and use the updated RAM timings for new SoMs.
Signed-off-by: Teresa Remmet
--
Changes in v2:
- Fix wrong RAM Timing values as pointed out by Yannic
Add helper function to read out the PCB revision of a PHYTEC SoM.
Signed-off-by: Teresa Remmet
---
Changes in v2:
- none
---
board/phytec/common/phytec_som_detection.c | 15 +++
board/phytec/common/phytec_som_detection.h | 5 +
2 files changed, 20 insertions(+)
diff --git a
Hello Yannic,
Am Mittwoch, dem 20.12.2023 um 09:19 +0100 schrieb Yannic Moog:
> In phytec_eeprom_data_init, after reading eeprom data into buffer, it
> is
> checked whether all bytes are 0x0 by iterating over chunks of the
> buffer. The offset, or index of the chunk, was never changed, leading
> t
Hello Wadim,
Am Montag, dem 10.06.2024 um 15:33 +0200 schrieb Wadim Egorov:
> From: Nathan Morrisson
>
> Add a fixed partitions node to the AM62x device tree so that it can
> be used to fixup the Linux device tree.
for which branch is this series?
Regards,
Teresa
>
> Signed-off-by: Nathan M
dr are board specific and
> need
> to be set in the board specific file. The env variable get_cmd also
> needs to be set in board specific files and can be set to tftp or
> dhcp.
>
> Signed-off-by: Benjamin Hahn
> Signed-off-by: Daniel Schultz
Reviewed-by: Teresa Remmet
>
ahn
> Signed-off-by: Daniel Schultz
Reviewed-by: Teresa Remmet
> ---
> board/phytec/phycore_imx8mp/phycore_imx8mp.env | 15 +++
> configs/phycore-imx8mp_defconfig | 6 +++---
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/board/
Am Mittwoch, dem 10.01.2024 um 14:35 +0100 schrieb Yannic Moog:
> phyGATE-Tauri-L-iMX8MM is a Gateway based on the phycore-imx8mm SoM.
> As a result, all the board code of the phycore-imx8mm is used.
> Device tree synced with kernel v6.7.
>
> Signed-off-by: Yannic Moog
Revi
Am Mittwoch, dem 10.01.2024 um 14:35 +0100 schrieb Yannic Moog:
> Add brief documentation on how to build a bootable U-Boot image for
> the
> phyGATE-Tauri-L.
>
> Signed-off-by: Yannic Moog
Reviewed-by: Teresa Remmet
> ---
> board/phytec/phycore_imx8mm/MAINTAINERS
Am Mittwoch, dem 10.01.2024 um 14:35 +0100 schrieb Yannic Moog:
> Add rst documentation files to the respective MAINTAINERS file for
> PHYTEC boards.
>
> Signed-off-by: Yannic Moog
Reviewed-by: Teresa Remmet
> ---
> board/phytec/phycore_imx8mm/MAINTAINERS | 1 +
> board/
Am Dienstag, dem 30.04.2024 um 20:42 -0600 schrieb Tom Rini:
> Remove from this board vendor directory and when needed
> add missing include files directly.
>
> Signed-off-by: Tom Rini
Acked-by: Teresa Remmet
> ---
> Cc: Martyn Welch
> Cc: Parthiban Nallathambi
> Cc
kept unchanged.
>
> Signed-off-by: Yannic Moog
Acked-by: Teresa Remmet
> ---
> arch/arm/dts/Makefile | 1 -
> arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 361 --
> --
> arch/arm/dts/imx8mp-phycore-som.dtsi | 323
data on default.
Alternative it is possible to set fix RAM size and speed over Kconfig.
Teresa
Benjamin Hahn (1):
board: phycore_imx8mp: enable setting 2GHz timings without RAM size
Teresa Remmet (3):
board: phytec: phycore-imx8mp: spl: Fix syle issue
board: phytec: phycore_imx8mp: Add
Use tabs instead of spaces.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/spl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/phytec/phycore_imx8mp/spl.c
b/board/phytec/phycore_imx8mp/spl.c
index df158024654e..492ce3b7ca6e 100644
--- a/board
From: Benjamin Hahn
make it possible to set the RAM timing frequency statically independent
from the RAM size. Fixed RAM timing frequency can be used while the
RAM size is still determined by the EEPROM image.
Signed-off-by: Benjamin Hahn
Signed-off-by: Teresa Remmet
---
board/phytec
: Benjamin Hahn
Co-developed-by: Yannic Moog
Signed-off-by: Yannic Moog
Co-developed-by: Yashwanth Varakala
Signed-off-by: Yashwanth Varakala
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/lpddr4_timing.c | 153 +++
board/phytec/phycore_imx8mp/lpddr4_timing.h | 16
We might not be able to always rely on the EEPROM introspection data.
So add a config option alternative which configures the RAM size
to a fix value.
We still try to read the EEPROM introspection data at this point.
So we can print the SoM information if available.
Signed-off-by: Teresa Remmet
are removed. U-Boot tweaks are kept unchanged.
>
> Signed-off-by: Yannic Moog
Acked-by: Teresa Remmet
> ---
> arch/arm/dts/Makefile | 2 -
> arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 460 ---
>
> arch/arm/dts
ection")
>
> Signed-off-by: Daniel Schultz
Reviewed-by: Teresa Remmet
> ---
> board/phytec/common/phytec_som_detection.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/board/phytec/common/phytec_som_detection.c
> b/board/phytec/commo
the valid value
> appropriately.
> Move the eeprom data to a new struct payload that holds
> the payload of the eeprom.
>
> Signed-off-by: Yannic Moog
> Signed-off-by: Daniel Schultz
Reviewed-by: Teresa Remmet
> ---
> board/phytec/common/imx8m_som_detection.c | 10 ++--
>
-by: Yannic Moog
> Signed-off-by: Daniel Schultz
Reviewed-by: Teresa Remmet
> ---
> board/phytec/common/imx8m_som_detection.c | 11 +++
> board/phytec/common/phytec_som_detection.c | 10 +++---
> 2 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --g
Am Freitag, dem 19.04.2024 um 08:55 -0700 schrieb Daniel Schultz:
> Add a generic function to apply overlays in our board code to not
> implement the same logic in different PHYTEC products.
>
> Signed-off-by: Daniel Schultz
Reviewed-by: Teresa Remmet
> ---
> b
Hello Benjamin,
Am Mittwoch, dem 31.01.2024 um 09:45 +0100 schrieb Benjamin Hahn:
> Signed-off-by: Benjamin Hahn
please add a proper patch description. Adding only a subject line
ist not enough.
Thanks,
Teresa
> ---
> arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 162
> ++
Hello Stefano,
Am Donnerstag, den 07.01.2021, 16:13 +0100 schrieb Stefano Babic:
> Hi Theresa,
>
> On 16.12.20 10:51, Teresa Remmet wrote:
> > Add initial support PHYTEC phyCORE-i.MX8MP SOM.
> >
> > Supported features:
> > - 2GB LPDDR4 RAM
>
SYS_MMC_ENV_DEV=2
> > > +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> > > +CONFIG_SPL_DM=y
> > > +CONFIG_CLK_COMPOSITE_CCF=y
> > > +CONFIG_CLK_IMX8MP=y
> > > +CONFIG_MXC_GPIO=y
> > > +CONFIG_DM_I2C=y
> > > +CONFIG_SYS_I2C_MXC=
Add initial support PHYTEC phyCORE-i.MX8MP SOM.
Supported features:
- 2GB LPDDR4 RAM
- eMMC
- external SD
- debug UART2
- watchdog
Signed-off-by: Teresa Remmet
---
Changes in v2:
- remove not needed spl board init
- remove ifdef from board_fit_config_name_match
Hello Heiko,
Am Montag, den 11.01.2021, 13:11 +0100 schrieb Heiko Schocher:
> Hello Teresa,
>
> Am 11.01.21 um 08:30 schrieb Teresa Remmet:
> > Add initial support PHYTEC phyCORE-i.MX8MP SOM.
> >
> > Supported features:
> > - 2GB LPDDR4 RAM
>
Add initial support PHYTEC phyCORE-i.MX8MP SOM.
Supported features:
- 2GB LPDDR4 RAM
- eMMC
- external SD
- debug UART2
- watchdog
Signed-off-by: Teresa Remmet
Reviewed-by: Heiko Schocher
---
Changes in v3:
- switched to accepted upstream kernel device tree
Add support PHYTEC phyCORE-i.MX8MM SOM.
Supported features:
- 2GB LPDDR4 RAM
- 1x 1Gbit Ethernet
- eMMC
- external SD
- debug UART3
- watchdog
- i2c eeprom
Signed-off-by: Teresa Remmet
---
arch/arm/dts/Makefile|1 +
arch/arm/dts/phycore-imx8mm-u-boot.dtsi
Hello Tom,
Am Donnerstag, den 20.08.2020, 09:22 -0400 schrieb Tom Rini:
> On Thu, Aug 20, 2020 at 08:55:30AM +0200, Teresa Remmet wrote:
>
> > Add support PHYTEC phyCORE-i.MX8MM SOM.
> >
> > Supported features:
> > - 2GB LPDDR4 RAM
> > - 1x 1Gbit Eth
Add support PHYTEC phyCORE-i.MX8MM SOM.
Supported features:
- 2GB LPDDR4 RAM
- 1x 1Gbit Ethernet
- eMMC
- external SD
- debug UART3
- watchdog
- i2c eeprom
Signed-off-by: Teresa Remmet
---
Changes in v2:
- Removed fdt_high to allow relocation
- Moved fdt_addr to 0x4800
arch/arm/dts
There is no separate SPL/TPL config for WATCHDOG_AUTOSTART.
So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog
working in spl again.
Signed-off-by: Teresa Remmet
---
drivers/watchdog/wdt-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog
Hello,
this patchstack includes phyCORE-i.MX8MP updates and the switch
to binman.
But also resynced the imx8mp.dtsi from kernel add introduced a
common imx8mp-u-boot.dtsi
Teresa
Teresa Remmet (9):
arm: dts: imx8mp: Resync imx8mp device tree include
arm: dts: imx8mp: Add common u-boot dtsi
Factor out the common node settings for dm-spl and dm-pre-reloc
and move them to imx8mp-u-boot.dtsi
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 39 +
.../imx8mp-phyboard-pollux-rdk-u-boot.dtsi| 39 +
arch/arm/dts/imx8mp-u
Sync imx8mp include with kernel commit:
d1689cd3c0f4 ("arm64: dts: imx8mp: Use the correct name for child node "snps,
dwc3"")
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp.dtsi | 146 +--
1 file changed, 141 insertions(+), 5 deleti
This update includes eqos support and debug uart changes.
Synced with kernel commit
846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 58 ++---
arch/arm/dts/imx8
With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4
Enable support for the fec ethernet on phyCORE-i.MX8MP.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/phycore-imx8mp.c | 14 +++
configs/phycore-imx8mp_defconfig | 7 ++
include/configs/phycore_imx8mp.h | 25
3 files
Increase VDD_ARM to prevent timing issues as VDD_SOC is
used in OD mode. Also increase GIC clock.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/spl.c | 11 ++-
configs/phycore-imx8mp_defconfig | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/board
Add missing pinctrl entry in spl.
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
index
Enable DVS1 control through PMIC_STBY_REQ.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/spl.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/board/phytec/phycore_imx8mp/spl.c
b/board/phytec/phycore_imx8mp/spl.c
index 815ca9badcba..19c486e55174 100644
Use now binman for image creation.
Signed-off-by: Teresa Remmet
---
.../imx8mp-phyboard-pollux-rdk-u-boot.dtsi| 105 ++
arch/arm/mach-imx/imx8m/Kconfig | 1 +
.../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++
configs/phycore-imx8mp_defconfig
Hello Marek,
Am Donnerstag, den 01.07.2021, 01:08 +0200 schrieb Marek Vasut:
> In case the iMX8M boot from eMMC boot partition and the primary image
> is corrupted, the BootROM is capable of starting a secondary image in
> the other eMMC boot partition as a fallback.
I would like to ask a more ge
Hello Fabio,
Am Donnerstag, den 01.07.2021, 08:24 -0300 schrieb Fabio Estevam:
> Hi Teresa,
>
> Your series looks great. Just a few comments on this patch.
thanks for your quick review.
>
> On Thu, Jul 1, 2021 at 6:47 AM Teresa Remmet
> wrote:
>
> > --- a/inclu
board config include
Teresa
Teresa Remmet (9):
arm: dts: imx8mp: Resync imx8mp device tree include
arm: dts: imx8mp: Add common u-boot dtsi
arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernel
board: phytec: phycore_imx8mp: Change debug UART
board: phytec: phycore_imx8mp: Add
Sync imx8mp include with kernel commit:
d1689cd3c0f4 ("arm64: dts: imx8mp: Use the correct name for child node "snps,
dwc3"")
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp.dtsi | 146 +--
1 file changed, 141 insertions(+), 5 deleti
Factor out the common node settings for dm-spl and dm-pre-reloc
and move them to imx8mp-u-boot.dtsi
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 39 +
.../imx8mp-phyboard-pollux-rdk-u-boot.dtsi| 39 +
arch/arm/dts/imx8mp-u
With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4
This update includes eqos support and debug uart changes.
Synced with kernel commit
846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 58 ++---
arch/arm/dts/imx8
Enable support for the fec ethernet on phyCORE-i.MX8MP.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/phycore-imx8mp.c | 14 ++
configs/phycore-imx8mp_defconfig | 7 +++
include/configs/phycore_imx8mp.h | 17 +
3 files
Increase VDD_ARM to prevent timing issues as VDD_SOC is
used in OD mode. Also increase GIC clock.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/spl.c | 11 ++-
configs/phycore-imx8mp_defconfig | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/board
Enable DVS1 control through PMIC_STBY_REQ.
Signed-off-by: Teresa Remmet
---
board/phytec/phycore_imx8mp/spl.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/board/phytec/phycore_imx8mp/spl.c
b/board/phytec/phycore_imx8mp/spl.c
index 815ca9badcba..19c486e55174 100644
Add missing pinctrl entry in spl.
Signed-off-by: Teresa Remmet
---
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
index
Use now binman for image creation.
Signed-off-by: Teresa Remmet
---
.../imx8mp-phyboard-pollux-rdk-u-boot.dtsi| 105 ++
arch/arm/mach-imx/imx8m/Kconfig | 1 +
.../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++
configs/phycore-imx8mp_defconfig
Hello Heiko,
Am Montag, den 05.07.2021, 06:58 +0200 schrieb Heiko Schocher:
> Hello Teresa,
>
> On 02.07.21 13:19, Teresa Remmet wrote:
> > With the first redesign the debug UART had changed from
> > UART2 to UART1.
> > As the first hardware revision is considered a
Hello Jagan,
Am Montag, den 05.07.2021, 11:01 +0530 schrieb Jagan Teki:
> On Fri, Jul 2, 2021 at 4:49 PM Teresa Remmet
> wrote:
> > Use now binman for image creation.
> >
> > Signed-off-by: Teresa Remmet
> > ---
> > .../imx8mp-phyb
nges in v2:
- [5/9] removed hardcoded serverip in environment
- [5/9] removed not needed fec eth defines in board config include
Teresa
Teresa Remmet (9):
arm: dts: imx8mp: Resync imx8mp device tree include
arm: dts: imx8mp: Add common u-boot dtsi
arm: dts: imx8mp-phyboard-po
Sync imx8mp include with kernel commit:
d1689cd3c0f4 ("arm64: dts: imx8mp: Use the correct name for child node "snps,
dwc3"")
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
Reviewed-by: Heiko Schocher
---
No changes in v2 and v3.
arch/arm/d
Factor out the common node settings for dm-spl and dm-pre-reloc
and move them to imx8mp-u-boot.dtsi
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
Reviewed-by: Heiko Schocher
---
Changes in v3:
- Moved binman nodes to common imx8mp-u-boot.dtsi
Changes in v2:
- none
arch/arm/dts
Increase VDD_ARM to prevent timing issues as VDD_SOC is
used in OD mode. Also increase GIC clock.
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
---
No changes in v2 or v3.
board/phytec/phycore_imx8mp/spl.c | 11 ++-
configs/phycore-imx8mp_defconfig | 1 +
2 files changed
This update includes eqos support and some minor changes.
Synced with kernel commit
412627f6ffe3 ("arm64: dts: imx8mp-phyboard-pollux-rdk: Add missing pinctrl
entry")
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
Reviewed-by: Heiko Schocher
---
Changes in v3:
- Don't
With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
Reviewed-by: Heiko Schocher
Enable support for the fec ethernet on phyCORE-i.MX8MP.
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
Reviewed-by: Heiko Schocher
---
Changes in v3:
- none
Changes in v2:
- removed hardcoded serverip in environment
- removed not needed fec eth defines in board config include
board
Enable DVS1 control through PMIC_STBY_REQ.
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
---
No changes in v2 or v3.
board/phytec/phycore_imx8mp/spl.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/board/phytec/phycore_imx8mp/spl.c
b/board/phytec
Add missing pinctrl entry in spl.
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
---
No changes in v2 or v3.
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
b/arch/arm/dts
Use now binman for image creation.
Signed-off-by: Teresa Remmet
Reviewed-by: Fabio Estevam
Reviewed-by: Heiko Schocher
---
Changes in v3:
- binman nodes have been moved to common dtsi so removed from this patch
Changes in v2:
- none
arch/arm/mach-imx/imx8m/Kconfig | 1
Hello Tim,
Am Mittwoch, den 14.07.2021, 15:42 -0700 schrieb Tim Harvey:
> On Fri, Jun 18, 2021 at 4:14 AM Teresa Remmet
> wrote:
> > There is no separate SPL/TPL config for WATCHDOG_AUTOSTART.
> > So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog
> &
There is no separate SPL/TPL config for WATCHDOG_AUTOSTART.
So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog
working in SPL again.
Fixes: 830d29ac3721 ("watchdog: Allow to use CONFIG_WDT without starting
watchdog")
Signed-off-by: Teresa Remmet
Reviewed-by: St
Hello Heiko,
Am Donnerstag, den 25.02.2021, 14:46 +0100 schrieb Heiko Schocher:
> Hello Peng, Teresa,
>
> I am just trying to get linux-stable 5.10.y kernel with current
> mainline
> U-Boot on the pyhcore imx8mp board up and running, and fail detecting
> sd
> card on usdhc2 in linux.
>
> With U-
Hello,
Am Freitag, den 21.08.2020, 09:55 +0200 schrieb Teresa Remmet:
> Add support PHYTEC phyCORE-i.MX8MM SOM.
>
> Supported features:
> - 2GB LPDDR4 RAM
> - 1x 1Gbit Ethernet
> - eMMC
> - external SD
> - debug UART3
> - watchdog
> - i2c eeprom
>
you for the patch.
Works for phyCORE-i.MX8MM and phyCORE-i.MX8MP.
Tested-by: Teresa Remmet
Regards,
Teresa
>
> Signed-off-by: Peng Fan
> ---
> board/phytec/phycore_imx8mm/spl.c | 12 ++--
> board/phytec/phycore_imx8mp/spl.c | 8
> configs/phycore-imx8mm_
and phyCORE-i.MX8MP.
Tested-by: Teresa Remmet
Regards,
Teresa
>
> Signed-off-by: Peng Fan
> ---
> board/phytec/phycore_imx8mm/spl.c | 19 ---
> board/phytec/phycore_imx8mp/spl.c | 19 ---
> 2 files changed, 38 deletions(-)
>
> diff --git
Am Freitag, dem 08.04.2022 um 11:25 +0800 schrieb Peng Fan (OSS):
> From: Peng Fan
>
> With SPL_DM_MMC and DM_MMC, the two macros not needed, drop it.
> CONFIG_SYS_FSL_USDHC_NUM
> CONFIG_SYS_FSL_ESDHC_ADDR
Thank you for the patch.
Acked-By: Teresa Remmet
Regards,
Teresa
: Teresa Remmet
---
arch/arm/dts/imx8mp-u-boot.dtsi | 17 -
.../imx8mp_evk/imximage-8mp-lpddr4.cfg | 2 +-
board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 2 +-
doc/board/nxp/imx8mp_evk.rst| 1 -
4 files changed, 18 insertions(+), 4
Am Dienstag, den 17.08.2021, 14:32 +0800 schrieb Ye Li:
> Since SPL has initialized clocks for bus and core. We don't need to
> set the default clocks for clock controller node.
>
> Signed-off-by: Ye Li
Tested-by: Teresa Remmet
> ---
> arch/arm/dts/imx8mp-u-boot
Am Mittwoch, den 25.08.2021, 12:56 -0300 schrieb Fabio Estevam:
> Hi Teresa,
>
> On Wed, Aug 25, 2021 at 12:25 PM Teresa Remmet
> wrote:
> > binman conversion made flashing flash.bin
> > and u-boot.itb necessary. Update binman config
> > to create a single flash.
: Teresa Remmet
Reviewed-by: Fabio Estevam
Reviewed-by: Heiko Schocher
---
Changes in v2:
- Added filename to spl node
- Use u-boot-spl-ddr.bin in the LOADER section
arch/arm/dts/imx8mp-u-boot.dtsi | 19 ++-
.../imx8mp_evk/imximage-8mp-lpddr4.cfg| 2
Hello Marcel,
Am Donnerstag, den 26.08.2021, 14:14 +0200 schrieb Marcel Ziswiler:
> From: Marcel Ziswiler
>
> With the move to using binman to generate SPL aka u-boot-spl-ddr.bin
> and
> U-Boot proper aka u-boot.itb every board now covers such
> configuration
> in its own U-Boot specific device
Add initial support PHYTEC phyCORE-i.MX8MP SOM.
Supported features:
- 2GB LPDDR4 RAM
- eMMC
- external SD
- debug UART2
- watchdog
Signed-off-by: Teresa Remmet
---
arch/arm/dts/Makefile|1 +
arch/arm/dts/phycore-imx8mp-u-boot.dtsi
{loadaddr} ${image}
> +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
a small nit here as you sort them alphabetically. "loadimage" and
"loadfdt" needs to be swapped.
besides of this:
Reviewed-by: Teresa Remmet
Tested-by: Teresa Remmet
Thanks!
Teresa
&g
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Move the default bootcmd from the defconfig to the board environment.
> No change in functionality.
>
> Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
> ---
> board/phytec/phycore_imx8mp/
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Add support for the redundant environment.
>
> Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
> ---
> configs/phycore-imx8mp_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
&
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Add logic for booting systems with the RAUC update mechanism. This
> can
> be reused by other phytec boards.
>
> Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
> ---
> include/env
Am Dienstag, dem 12.03.2024 um 09:59 +0100 schrieb Leonard Anderweit:
> Add RAUC boot logic to the environment. This is the first board to
> utilize this environment.
>
> Signed-off-by: Leonard Anderweit
Tested-by: Teresa Remmet
> ---
> board/phytec/phycore_imx8mp/phyc
This patchstack contains mainly cleanup for phyCORE-i.MX8MM but
also adds:
* SPI NOR flash support
* clk command
* binman support
Teresa
Teresa Remmet (9):
board: phytec: phycore_imx8mm: Clean up spl
include: configs: phycore_imx8mm: Remove hard coded network settings
include: configs
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