Add ODROID-M1 board support. Board device tree rk3568-odroid-m1.dts
from v6.4.
Signed-off-by: Stefan Agner
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi | 29 +
arch/arm/dts/rk3568-odroid-m1.dts | 744 ++
configs
On 2023-07-05 18:24, Jonas Karlman wrote:
> Hi Stefan,
> On 2023-07-05 18:16, Stefan Agner wrote:
>> Add ODROID-M1 board support. Board device tree rk3568-odroid-m1.dts
>> from v6.4.
>
> I sent out a series that add support for ODROID-M1 a few days ago.
> Please see h
e. I've also tested it on an ODORID-M1 with 8GB of memory, it
boots fine from SD card.
Reviewed-by: Stefan Agner
Tested-by: Stefan Agner
One thing I've noticed is that USB isn't working when I use the stock
SPL (2017.09) running from the SPI RAM and upstream U-Boot (by writing
On 2023-07-06 07:08, Jonas Karlman wrote:
> On 2023-07-06 01:27, Stefan Agner wrote:
>> On 2023-07-02 22:47, Jonas Karlman wrote:
>>> Hardkernel ODROID-M1 is a single board computer with a RK3568B2 SoC,
>>> a slightly modified version of the RK3568 SoC.
>>>
&g
Hi Andrew,
On 2022-03-29 18:58, Andrew Scull wrote:
> When parsing the `ranges` DT node, check that both extremes of the
> regions are addressable without overflow. This assumption can then be
> safely made when processing the regions.
I've bisected this patch to break USB support on 32-bit Raspb
Hi Ivan,
On 2023-12-18 22:03, Ivan T. Ivanov wrote:
> Hi,
>
> These patches are adding basic support for RPi5.
> They are based on v2 series from Dmitry Malkin[1].
>
> With them I am able to _start_ current openSUSE
> Tumbleweed without modification. They are still
> a lot of things to be added
Hi Jonas,
On 2023-10-01 21:17, Jonas Karlman wrote:
> Add rk_gmac_ops and other special handling that is needed for GMAC to
> work on RK3588.
>
> rk_gmac_ops was ported from linux commits:
> 2f2b60a0ec28 ("net: ethernet: stmmac: dwmac-rk: Add gmac support for rk3588")
> 88619e77b33d ("net: stmmac
ly
32-bit accesses in xhci_writeq/xhci_readq").
Cc: Sylwester Nawrocki
Cc: Zhikang Zhang
Cc: Nicolas Saenz Julienne
Cc: Matthias Brugger
Signed-off-by: Stefan Agner
---
drivers/nvme/nvme.h | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nv
On 2020-12-30 02:36, Bin Meng wrote:
> Hi Stefan,
>
> On Wed, Dec 30, 2020 at 3:37 AM Stefan Agner wrote:
>
> The tag is wrong. Should be nvme:
Thanks for pointing out. Will send a v2.
FWIW, the send to amlogic ML was accidentially.
--
Stefan
>
>>
>> There mi
uot;).
Cc: Sylwester Nawrocki
Cc: Nicolas Saenz Julienne
Cc: Matthias Brugger
Reviewed-by: Stefan Roese
Reviewed-by: Bin Meng
Signed-off-by: Stefan Agner
---
Changes in v2:
- Fix subject and message to reflect NVMe change
drivers/nvme/nvme.h | 8
1 file changed, 8 deletions(-)
di
Hi,
I noticed a quite common freeze when running 32-bit U-Boot 2020.01
(rpi_4_32b_defconfig) on a 2GB RPi4 model:
U-Boot 2020.01 (Aug 07 2020 - 13:00:23 +)
DRAM: 1.9 GiB
This happens fairly often, I would say 4 out of 5 boot tries. However,
if it boots, everything seems to run fine.
The
2020 - 22:02:31 +)
DRAM: 3.9 GiB
I still think there is something wrong with caching. From what I
understand caches are enabled by the RPi (4) firmware. Is it safe to run
32-bit ARM U-Boot with enabled caches?
--
Stefan
On 2020-08-23 19:06, Stefan Agner wrote:
> Hi,
>
> I notice
The property reg-shift with the same value is present in the base
device tree already. Remove unnecessary node from rk3288-tinker.dts.
Signed-off-by: Stefan Agner
---
arch/arm/dts/rk3288-tinker.dts | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm
The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.
Cc: Jonas Karlman
Signed-off-by: Stefan Agner
---
arch/arm/dts/rk3288-tinker-u-boot.dtsi | 7 +++
arch/arm/dts/rk3288-tinker.dts | 7
.9 GiB
>>
>>
>> I still think there is something wrong with caching. From what I
>> understand caches are enabled by the RPi (4) firmware. Is it safe to run
>> 32-bit ARM U-Boot with enabled caches?
>>
>> --
>> Stefan
>>
>> On 2020-08-23 19:06,
ream Linux commit c183c406c432 ("arm64: dts: meson: fix PHY
deassert timing requirements").
Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner
---
arch/arm/dts/meson-g12b-odroid-n2.dtsi | 2 +-
arch/arm/dts/meson-gxbb-nanop
On 2021-04-07 15:31, Neil Armstrong wrote:
> Hi,
>
> On 06/04/2021 19:47, Stefan Agner wrote:
>> The sync of the device tree and dt-bindings from Linux v5.6-rc2
>> 11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
>> ODROID-C2.
>>
>>
On 2021-04-07 16:29, Neil Armstrong wrote:
> On 07/04/2021 16:21, Stefan Agner wrote:
>> On 2021-04-07 15:31, Neil Armstrong wrote:
>>> Hi,
>>>
>>> On 06/04/2021 19:47, Stefan Agner wrote:
>>>> The sync of the device tree and dt-bindings from
rt the new bindings in the PHY node.
Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner
---
arch/arm/dts/meson-gxbb-odroidc2.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts
b/arc
rt the new bindings in the PHY node.
Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Stefan Agner
---
arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/meson-gxbb-odroidc2-u-b
Hi Nicolas,
On 2020-06-29 18:37, Nicolas Saenz Julienne wrote:
> Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
> loaded explicitly. Earlier versions didn't need that as they where using
> an EEPROM for that purpose. This series takes care of setting up the
> relevant infr
the noise! And thanks for all your work!
--
Stefan
On 2020-07-19 02:37, Stefan Agner wrote:
> Hi Nicolas,
>
> On 2020-06-29 18:37, Nicolas Saenz Julienne wrote:
>> Newer revisions of the RPi4 need their xHCI chip, VL805, firmware to be
>> loaded explicitly. Earlier version
On 2019-11-04 12:56, Igor Opaniuk wrote:
> From: Igor Opaniuk
>
> Take over maintainership for colibri_imx6/imx6ull/t30/vf modules.
>
> Signed-off-by: Igor Opaniuk
Acked-by: Stefan Agner
Thanks for looking after those boards!
--
Stefan
> ---
>
> board
On 2020-07-19 12:06, Nicolas Saenz Julienne wrote:
> Hi Stefan,
>
> On Sun, 2020-07-19 at 02:37 +0200, Stefan Agner wrote:
>> Hi Nicolas,
>>
>> On 2020-06-29 18:37, Nicolas Saenz Julienne wrote:
>> > Newer revisions of the RPi4 need their xHCI chip, VL805,
On 2020-09-14 10:15, Matthias Brugger wrote:
> On 10/09/2020 23:12, Stefan Agner wrote:
>> On 2020-09-07 16:36, Peter Robinson wrote:
>>>> Any thoughts on this issue?
>>>
>>> Any reason why you're using 2020.01 and not at least 2020.07, or at
>>
On 2020-09-14 10:15, Matthias Brugger wrote:
> On 10/09/2020 23:12, Stefan Agner wrote:
>> On 2020-09-07 16:36, Peter Robinson wrote:
>>>> Any thoughts on this issue?
>>>
>>> Any reason why you're using 2020.01 and not at least 2020.07, or at
>>
On 2020-09-19 23:20, Sean Anderson wrote:
> On 9/19/20 7:55 AM, Stefan Agner wrote:
>> On 2020-09-14 10:15, Matthias Brugger wrote:
>>> On 10/09/2020 23:12, Stefan Agner wrote:
>>>> On 2020-09-07 16:36, Peter Robinson wrote:
>>>>>> Any thoughts
retry count typically works.
Increase retries to 20 for a startup time of up to 2s.
Signed-off-by: Stefan Agner
---
common/usb_storage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/usb_storage.c b/common/usb_storage.c
index ff25441995..04910de21f 100644
--- a/common
On 2020-09-20 21:01, Stefan Agner wrote:
> A JMicron JMS583 based NVMe to USB 3.1 enclosure connected to a Raspberry
> Pi 4 fails to enumerate as a USB Mass Storage device on first try:
>
> ...
> startig USB...
> Bus xhci_pci: Register 5000420 NbrPorts 5
> Starting t
If the CROS device class is not compiled in, uclass returns not
supported. Ignore this case as well.
This avoids boot failures on ODROID-XU4 without CONFIG_CROS_EC
ending with:
cros-ec communications failure -96
Please reset with Power+Refresh
Cannot init cros-ec device
Signed-off-by: Stefan
Hi,
When trying to boot rpi_4_32b_defconfig of U-Boot 2020.10 (or master)
using a USB flash drive, U-Boot hangs early at:
U-Boot 2020.10 (Nov 20 2020 - 10:25:26 +0100)
DRAM: 3.9 GiB
The weird thing is that at this point U-Boot does not access USB/SD card
at all, still it matters if it got boo
Move loading of socinfo into a separate function so the value can be
reused later.
Signed-off-by: Stefan Agner
---
arch/arm/mach-meson/board-info.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board
From: Pascal Vizeli
Add SoC revision to environment. This can be useful to select the
correct device tree at runtime (N2/N2+).
Signed-off-by: Pascal Vizeli
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-meson/boot.h | 4
arch/arm/mach-meson/board-info.c | 12
set to 270° it is detected with 8-bit bus width and is
working fine accross all temperatures.
Signed-off-by: Stefan Agner
---
Hi Neil,
I debugged this issue today on an ODROID N2+ not booting reliably. I am
not sure if we can safely switch to 270° for all SoCs with
amlogic,meson-axg-mmc, but I
On 2020-12-15 06:19, Jaehoon Chung wrote:
> Hi,
>
> On 12/15/20 3:58 AM, Neil Armstrong wrote:
>> Hi,
>>
>> On 07/12/2020 18:15, Stefan Agner wrote:
>>> Amlogic AGX SoCs seem to have issue communicating with some eMMC
>>> devices (in particular wit
When parsing a path with a leading slash, the root inode was freed which
lead
to a crash. Path parsing is now improved and allows leading slashs like
other
filesystem commands (e.g. ext4load).
Signed-off-by: Stefan Agner
---
fs/btrfs/btrfs.c | 6 +++---
1 file changed, 3 insertions(+), 3
Reading the super block leads to data abort crashes. Enabling the no
unaligned
option works around this. Since the format of the super block is fixed
by
the on-disk format unaligned access might by necessary in order to have
btrfs
support at all.
Signed-off-by: Stefan Agner
---
fs/btrfs
The function btrfs_mangle_name limited path lenght to 20 characters.
Since
the command parsing already checks spaces, the function is not needed at
all.
---
fs/btrfs/btrfs.c | 44 +---
1 file changed, 1 insertion(+), 43 deletions(-)
diff --git a/fs/btrfs
is also available at Github:
https://github.com/falstaff84/u-boot
Ali, could you review those patch and include it in your next
submission? When
is your next submission planned? I'm happy to help testing/fixing
remaining
problems...
Best regards,
Stefan Agner
Stefan Agner (3):
btrfs
Am 2013-07-11 15:54, schrieb Justin Waters:
> Give the user the ability to disable NAND support by defining
> CONFIG_NO_NAND. This will allow custom hardware to easily support
> this configuration.
If NAND is not enabled, we could also ifdef the SPI/MTD/CMD_FS
configurations since they are not use
d support for eMMC environment
> am335x_evm: Add am335x_boneblack variant
Applied your patches on v2013.07-rc3 and compiled the beaglebone target.
Works fine on my BeagleBone Black.
Tested-by: Stefan Agner
--
Stefan
___
U-Boot mailing list
U-Bo
forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.
Signed-off-by: Stefan Agner
---
drivers/usb/host/ehci-tegra.c | 22 ++
1 file changed
forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.
Also use the slightly different bit fields of first USB, (USBD)
on Tegra 2.
Signed-off-by: Stefan Agner
Am 2014-02-14 23:45, schrieb Stefan Agner:
> /* Select ULPI parallel interface */
> - clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
> + if (!controller->has_hostpc) {
> + clrsetbits_le32(
Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.
Signed-off-by: Stefan Agner
---
drivers/usb/host/ehci-tegra.c | 3 +++
1 file changed, 3
uld
also profit from this merge, if yes, I think then its definitely
worth doing it.
Stefan Agner (3):
usb: tegra: fix USB2 powerdown for Tegra30 and later
usb: tegra: fix PHY configuration
usb: tegra: combine header file
arch/arm/include/asm/arch-tegra/usb.h| 215 +
Combine the Tegra USB header file into one header file for all SoCs.
Use ifdef to account for the difference, especially Tegra20 is quite
different from newer SoCs. This avoids duplication especially
between Tegra30 and newer devices.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch
use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-tegra/usb.h | 5 -
arch/arm/include/asm/arch-tegra20/usb.h | 7 ++-
drivers/usb/host/ehci
Am 2014-02-18 20:27, schrieb Stephen Warren:
> On 02/16/2014 12:50 PM, Stefan Agner wrote:
>> +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
>> +/* USB2_IF_ULPI_TIMING_CTRL_0 */
>> +#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
>>
use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.
Reviewed-by: Stephen Warren
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-tegra/usb.h | 5 -
arch/arm/include/asm/arch-tegra20/usb.h | 7
ces between USBD and other USB ports into account
port_sc1
---
Stefan Agner (3):
usb: tegra: fix USB2 powerdown for Tegra30 and later
usb: tegra: fix PHY configuration
usb: tegra: combine header file
arch/arm/include/asm/arch-tegra/usb.h| 211 ++-
arch/arm/inclu
Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.
Acked-by: Stephen Warren
Signed-off-by: Stefan Agner
---
drivers/usb/host/ehci-tegra.c
Combine the Tegra USB header file into one header file for all SoCs.
Use ifdef to account for the difference, especially Tegra20 is quite
different from newer SoCs. This avoids duplication especially
between Tegra30 and newer devices.
Reviewed-by: Stephen Warren
Signed-off-by: Stefan Agner
Am 2014-02-24 19:43, schrieb Stephen Warren:
> Are you planning on sending a later patch which removes
> arch/arm/include/asm/arch-tegra124/usb.h too?
I did not noticed that file, I created the patch on top of upstream
U-Boot. In which branch/repo can I find this file? git.denx.de seems to
be down
use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.
Reviewed-by: Stephen Warren
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-tegra/usb.h | 5 -
arch/arm/include/asm/arch-tegra20/usb.h | 7
erging of the header files
Changes since v1:
- Take differences between USBD and other USB ports into account
port_sc1
---
Stefan Agner (3):
usb: tegra: fix USB2 powerdown for Tegra30 and later
usb: tegra: fix PHY configuration
usb: tegra: combine header file
arch/arm/include/asm/arch-
Combine the Tegra USB header file into one header file for all SoCs.
Use ifdef to account for the difference, especially Tegra20 is quite
different from newer SoCs. This avoids duplication, mainly for
Tegra30 and newer devices.
Reviewed-by: Stephen Warren
Signed-off-by: Stefan Agner
---
arch
Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.
Acked-by: Stephen Warren
Signed-off-by: Stefan Agner
---
drivers/usb/host/ehci-tegra.c
Hi Tom,
> Stephen Warren (1):
> ARM: tegra: make all I2C ports open-drain
>
> board/nvidia/dalmore/pinmux-config-dalmore.h | 16
> board/nvidia/venice2/pinmux-config-venice2.h | 16
> 2 files changed, 16 insertions(+), 16 deletions(-)
Is there something h
Am 2014-03-28 16:54, schrieb Tom Warren:
> Have they all been ACKed? Sorry, been really busy with normal NVIDIA stuff.
They have been ACKed, see
http://lists.denx.de/pipermail/u-boot/2014-March/175302.html
and tested by Stephen,
http://lists.denx.de/pipermail/u-boot/2014-March/174662.html
> I
Am 2014-05-14 23:29, schrieb Anthony Felice:
> Removed settings in unsupported register fields. They didn’t
> do anything, and in most cases, were not documented in the
> reference manual.
>
> Changed register settings to comply with JEDEC required values.
>
> Changed timing parameters because th
This adds board support for the Toradex Colibri T30 module.
Working functions:
- SD card boot
- eMMC environment and boot
- USB host/USB client (on the dual role port)
- Network (via ASIX USB)
Signed-off-by: Stefan Agner
---
arch/arm/Kconfig | 4 +
arch/arm
Hi Simon,
Am 2014-07-31 19:41, schrieb Simon Glass:
> Hi Stefan,
>
> On 31 July 2014 18:36, Stefan Agner wrote:
>>
>> This adds board support for the Toradex Colibri T30 module.
>>
>
> A few quick questions below...
>
>
>>
>> Working fun
Am 2014-07-31 23:55, schrieb Simon Glass:
> Hi Stefan,
>
> On 31 July 2014 19:00, Stefan Agner wrote:
>> Hi Simon,
>>
>> Am 2014-07-31 19:41, schrieb Simon Glass:
>>> Hi Stefan,
>>>
>>> On 31 July 2014 18:36, Stefan Agner wrote:
>>
Am 2014-07-31 20:21, schrieb Stephen Warren:
> On 07/31/2014 11:36 AM, Stefan Agner wrote:
>> This adds board support for the Toradex Colibri T30 module.
>>
>> Working functions:
>> - SD card boot
>> - eMMC environment and boot
>> - USB host/USB client (o
Am 2014-08-04 19:16, schrieb Tom Rini:
> On Mon, Aug 04, 2014 at 11:02:28AM -0600, Stephen Warren wrote:
>> On 08/02/2014 08:09 AM, Stefan Agner wrote:
>> >Am 2014-07-31 20:21, schrieb Stephen Warren:
>> >>On 07/31/2014 11:36 AM, Stefan Agner wrote:
>> >&g
Am 2014-08-04 19:02, schrieb Stephen Warren:
> On 08/02/2014 08:09 AM, Stefan Agner wrote:
>> Am 2014-07-31 20:21, schrieb Stephen Warren:
>>> On 07/31/2014 11:36 AM, Stefan Agner wrote:
>>>> This adds board support for the Toradex Colibri T30 module.
>>>&
This adds board support for the Toradex Colibri T30 module.
Working functions:
- SD card boot
- eMMC environment and boot
- USB host/USB client (on the dual role port)
- Network (via ASIX USB)
Signed-off-by: Stefan Agner
---
This patch requires Stephens patch "ARM: tegra: enable DF
Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 14 ++
arch/arm/include/asm/arch-vf610/imx-regs.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/arch/arm
This patch set adds NAND Flash Controller (NFC) support for
Freescale Vybrid ARM SoCs (vf610).
The driver is based on Bill Pringlemeirs prelineary patch sent
in January 2014 to the MTD mailing list:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-January/226623.html
Stefan Agner (4
Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 34 +++
arch/arm/include/asm/imx-common
This adds initial support for Freescale NFC (NAND Flash Controller).
The IP is used in ARM based Vybrid SoCs as well as on some PowerPC
devices. This driver is only tested on Vybrid.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/fsl_nfc.c | 676
configuration block (BCB).
Signed-off-by: Stefan Agner
---
board/freescale/vf610twr/vf610twr.c | 47 ++---
configs/vf610twr_defconfig | 2 +-
configs/vf610twr_nand_defconfig | 3 +++
include/configs/vf610twr.h | 43
Am 2014-08-12 00:33, schrieb Scott Wood:
> On Wed, 2014-08-06 at 10:59 +0200, Stefan Agner wrote:
>> This adds initial support for Freescale NFC (NAND Flash Controller).
>> The IP is used in ARM based Vybrid SoCs as well as on some PowerPC
>> devices. This driver is
Am 2014-08-13 00:58, schrieb Bill Pringlemeir:
> On 12 Aug 2014, scottw...@freescale.com wrote:
>
>> On Tue, 2014-08-12 at 23:13 +0200, Stefan Agner wrote:
>>> Am 2014-08-12 00:33, schrieb Scott Wood:
>>>> On Wed, 2014-08-06 at 10:59 +0200, Stefan Agner wrote:
&g
Am 2014-08-13 00:58, schrieb Bill Pringlemeir:
[snip]
> +static u32 nfc_read(struct mtd_info *mtd, uint reg)
> +{
> + struct fsl_nfc *nfc = mtd_to_nfc(mtd);
> +
> + if (reg == NFC_FLASH_STATUS1 ||
> + reg == NFC_FLASH_STATUS2 ||
> + reg == NFC_IRQ_STATUS)
> +
Am 2014-08-13 17:14, schrieb Bill Pringlemeir:
> On 13 Aug 2014, ste...@agner.ch wrote:
>
>> Am 2014-08-13 00:58, schrieb Bill Pringlemeir:
>> [snip]
>>> +static u32 nfc_read(struct mtd_info *mtd, uint reg)
>>> +{
>>> + struct fsl_nfc *nfc = mtd_to_nfc(mtd);
>>> +
>>> +
Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 14 ++
arch/arm/include/asm/arch-vf610/imx-regs.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/arch/arm
configuration block (BCB).
Signed-off-by: Stefan Agner
---
board/freescale/vf610twr/vf610twr.c | 47 ++---
configs/vf610twr_defconfig | 2 +-
configs/vf610twr_nand_defconfig | 3 +++
include/configs/vf610twr.h | 46
the amount of
written bits at all.
Performance numbers:
V1 => optimized count_written_bits
Read empty pages: 0.8MiB/s => 1.4MiB/s
V1 => optimized memcpy => optimized page_read/page_write
Read full pages: 3.6MiB/s => 7MiB/s => 10.3MiB/s
Stefan Agner (4):
arm: vf610: add NFC pi
Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 34 +++
arch/arm/include/asm/imx-common
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
However, this driver is only tested on Vybrid.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/Makefile| 1 +
drivers/mtd/nand/vf610_nfc.c
Am 2014-07-22 00:42, schrieb Stefan Agner:
> Am 2014-05-14 23:29, schrieb Anthony Felice:
>> Removed settings in unsupported register fields. They didn’t
>> do anything, and in most cases, were not documented in the
>> reference manual.
>>
>> Changed register setti
Am 2014-08-14 23:12, schrieb Bill Pringlemeir:
>> On 14 Aug 2014, ste...@agner.ch wrote:
>>
>> This adds initial support for Freescale NFC (NAND Flash Controller)
>> found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
>> However, this driver is only tested on Vybrid.
>
> This is only
boot configuration block
(BCB).
Signed-off-by: Stefan Agner
---
board/freescale/vf610twr/vf610twr.c | 47 ++---
configs/vf610twr_defconfig | 2 +-
configs/vf610twr_nand_defconfig | 3 +++
include/configs/vf610twr.h | 46
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
The driver is called vf610_nfc since this is the first supported
and tested hardware platform supported by the driver.
Signed-off-by: Stefan Agner
---
dr
MiB/s => 10.3MiB/s => 11.3MiB/s
Stefan Agner (4):
arm: vf610: add NFC pin mux
arm: vf610: add NFC clock support
mtd: nand: add Freescale vf610_nfc driver
arm: vf610: add NAND support for vf610twr
arch/arm/include/asm/arch-vf610/crm_regs.h| 14 +
arch/arm/include/asm/arch-vf610/imx-reg
Add pin mux for vf610 NAND Flash Controller (NFC). NAND can be
connected using 8 or 16 data lines, this patch adds pin mux entries
for all of the 16 possible data lines.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 34 +++
arch/arm
Add vf610 NFC (NAND Flash Controller) clock support and enable them
at board initialization time.
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-vf610/crm_regs.h | 14 ++
arch/arm/include/asm/arch-vf610/imx-regs.h | 1 +
2 files changed, 15 insertions(+)
diff --git a
clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.
Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.
Signed-off-by: Stefan Agner
---
drivers/serial
thresholds
and flushes them.
Signed-off-by: Stefan Agner
---
drivers/serial/serial_lpuart.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 96173ca..0a5e159 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers
Am 2014-08-18 18:38, schrieb Bill Pringlemeir:
> On 18 Aug 2014, ste...@agner.ch wrote:
>
>> Am 2014-08-14 23:12, schrieb Bill Pringlemeir:
On 14 Aug 2014, ste...@agner.ch wrote:
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Powe
assle to calculate whether the page is affected or not,
>> but set the page buffer unconditionally to invalid instead.
>>
>> Signed-off-by: Stefan Agner
>> ---
>> This are two bug fixes which would be nice if they would still
>> make it into 2015.04...
>>
nand dump command returns the data from the buffer,
>> > while in fact the page is erased (0xff).
>> >
>> > Avoid the hassle to calculate whether the page is affected or not,
>> > but set the page buffer unconditionally to invalid instead.
>> >
>
On 2015-03-30 22:48, Scott Wood wrote:
> On Mon, 2015-03-30 at 22:40 +0200, Stefan Agner wrote:
>> On 2015-03-30 22:34, Scott Wood wrote:
>> > On Mon, 2015-03-30 at 13:02 -0400, Bill Pringlemeir wrote:
>> >> On 24 Mar 2015, ste...@agner.ch wrote:
>> >>
&
On 2015-03-31 00:15, Scott Wood wrote:
> On Mon, 2015-03-30 at 23:26 +0200, Stefan Agner wrote:
>> On 2015-03-30 22:48, Scott Wood wrote:
>> > What is special about this controller, that caching makes sense here but
>> > not on other controllers? If it makes sense
upport
>
> Tested on Colibri VF50/VF61 booting using serial loader over UART.
>
> Signed-off-by: Stefan Agner
> Signed-off-by: Sanchayan Maity
> ---
> arch/arm/Kconfig | 5 +
> arch/arm/include/asm/arch-vf610/imx-regs.h | 5 +
> bo
To improve performance we remember the current page in the buffer
and avoid reading it twice. This implicit page cache increases
complexity while does not increase performance in real world cases.
This patch removes that feature.
---
As discussed in the other patchset...
http://thread.gmane.org/gma
Implement read of OOB area only. When using column and sector size
properties, only parts of the page can be read. However, this works
only when hardware ECC is disabled, otherwise the ECC engine would
ruin the data in the buffer. To allow OOB only reads, three points
had to be addressed:
- Set ECC
On 2015-04-03 01:48, Scott Wood wrote:
> On Tue, 2015-03-31 at 11:02 -0400, Bill Pringlemeir wrote:
>> On 2015-03-31 00:15, Scott Wood wrote:
>>
>> > Especially since you'd be doing one write rather than four full-page
>> > "partial" writes. Surely the bottleneck here is the NAND chip itself,
>> >
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