On 2020-12-30 02:36, Bin Meng wrote:
> Hi Stefan,
>
> On Wed, Dec 30, 2020 at 3:37 AM Stefan Agner <ste...@agner.ch> wrote:
>
> The tag is wrong. Should be nvme:
Thanks for pointing out. Will send a v2.
FWIW, the send to amlogic ML was accidentially.
--
Stefan
>
>>
>> There might be hardware configurations where 64-bit data accesses
>> to NVMe registers are not supported properly. This patch removes
>> the readq/writeq so always two 32-bit accesses are used to read/write
>> 64-bit NVMe registers, similarly as it is done in Linux kernel.
>>
>> This patch fixes operation of NVMe devices on RPi4 Broadcom
>> BCM2711 SoC based board, where the VL805 USB XHCI controller is
>> connected to the PCIe Root Complex, which is attached to the system
>> through the SCB bridge.
>>
>> Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
>> the 64-bit wide register accesses initiated by the CPU are not properly
>> translated to a sequence of 32-bit PCIe accesses.
>> nvme_readq(), for example, always returns same value in upper and lower
>> 32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail
>> probing.
>>
>> This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only
>> 32-bit accesses in xhci_writeq/xhci_readq").
>>
>> Cc: Sylwester Nawrocki <s.nawro...@samsung.com>
>> Cc: Zhikang Zhang <zhikang.zh...@nxp.com>
>> Cc: Nicolas Saenz Julienne <nsaenzjulie...@suse.de>
>> Cc: Matthias Brugger <mbrug...@suse.com>
>> Signed-off-by: Stefan Agner <ste...@agner.ch>
>> ---
>>
>> drivers/nvme/nvme.h | 8 --------
>> 1 file changed, 8 deletions(-)
>>
>
> Otherwise, LGTM:
>
> Reviewed-by: Bin Meng <bmeng...@gmail.com>
