> > Subject: [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig option
> >
> > There is no need to expose RISCV_NDS to the Kconfig menu as it is an
> > ax25-specific option.
> >
Hi Bin
Can you explain why there is no need to expose RISCV_NDS here ?
Rick
> > Signed-off-by: Bin Meng
>
Hi Bin
Bin Meng 於 2018年12月11日 週二 下午3:17寫道：
>
> Hi Rick,
>
> On Tue, Dec 11, 2018 at 3:06 PM Rick Chen wrote:
> >
> > > > Subject: [PATCH v2 06/20] riscv: ax25: Hide the ax25-specific Kconfig
> > > > option
> > > >
> > > > Th
Bin Meng 於 2018年12月12日 週三 下午5:37寫道：
>
> Hi Rick,
>
> On Wed, Dec 12, 2018 at 5:02 PM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2018年12月11日 週二 下午3:17寫道：
> > >
> > > Hi Rick,
> > >
> > > On Tue, Dec 11, 2018 at 3:06
> > From: Jean-Jacques Hiblot [mailto:jjhib...@ti.com]
> > Sent: Wednesday, December 12, 2018 8:00 PM
> > To: Tom Rini
> > Cc: U-Boot; Rick Jian-Zhi Chen(陳建志)
> > Subject: Re: [U-Boot] policy regarding unused code
> >
> > Tom, Rick,
> >
> > On 11/12/2018 19:17, Tom Rini wrote:
> > > On Tue, Dec 11,
Hi Bin
Bin Meng 於 2018年12月12日 週三 下午10:16寫道：
>
> Hi Rick,
>
> On Wed, Dec 12, 2018 at 5:56 PM Rick Chen wrote:
> >
> > Bin Meng 於 2018年12月12日 週三 下午5:37寫道：
> > >
> > > Hi Rick,
> > >
> > > On Wed, Dec 12, 2018 at 5:02 PM Rick Chen wro
t; > "andi %0, t1, 0x01\n\t"
> > @@ -81,7 +81,7 @@ int dcache_status(void) {
> > int ret = 0;
> >
> > -#ifdef CONFIG_RISCV_NDS
> > +#ifdef CONFIG_RISCV_NDS_CACHE
> > asm volatile (
> > "csrr t1, mcache_ctl\n\t"
> > "andi %0, t1, 0x02\n\t"
> > diff --git a/board/AndesTech/ax25-ae350/Kconfig
> > b/board/AndesTech/ax25-ae350/Kconfig
> > index bb69ea3..44cb302 100644
> > --- a/board/AndesTech/ax25-ae350/Kconfig
> > +++ b/board/AndesTech/ax25-ae350/Kconfig
> > @@ -21,4 +21,8 @@ config ENV_SIZE
> > config ENV_OFFSET
> > default 0x14 if ENV_IS_IN_SPI_FLASH
> >
> > +config BOARD_SPECIFIC_OPTIONS # dummy
> > + def_bool y
> > + select RISCV_NDS
> > +
> > endif
Reviewed-by: Rick Chen
> > --
> > 2.7.4
>
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Hi Bin
> > From: Bin Meng [mailto:bmeng...@gmail.com]
> > Sent: Friday, December 14, 2018 9:22 AM
> > To: Rick Jian-Zhi Chen(陳建志); Simon Glass; Lukas Auer; Anup Patel; U-Boot
> > Mailing List
> > Subject: Re: [PATCH v5 00/25] riscv: Adding RISC-V CPU and timer driver
> >
> > Hi Rick,
> >
> > On We
Hi Anup
> > From: Anup Patel [mailto:a...@brainfault.org]
> > Sent: Friday, December 14, 2018 5:23 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer
> > Cc: Alexander Graf; Palmer Dabbelt; Atish Patra; Christoph Hellwig; U-Boot
> > Mailing List
> > Subject: Re: [PATCH v2 0/2] SiFive UART su
Hi Bin
Bin Meng 於 2018年12月17日 週一 上午11:32寫道：
>
> Hi Rick,
>
> On Mon, Dec 17, 2018 at 11:21 AM Andes wrote:
> >
> > From: Rick Chen
> >
> > Remove cpu name from the defconfig naming.
> > Because other cpus maybe run on AE350 platform.
> > So onl
Hi Anup
Anup Patel 於 2018年12月17日 週一 下午12:15寫道：
>
> On Mon, Dec 17, 2018 at 7:21 AM Rick Chen wrote:
> >
> > Hi Anup
> >
> > > > From: Anup Patel [mailto:a...@brainfault.org]
> > > > Sent: Friday, December 14, 2018 5:23 PM
> > > >
Hi Bin
Bin Meng 於 2018年12月18日 週二 上午10:12寫道：
>
> Hi Rick,
>
> On Tue, Dec 18, 2018 at 9:51 AM Andes wrote:
> >
> > From: Rick Chen
> >
> > Rename
> > a25-ae350_32_defconfig as ae350_rv32_defconfig
> > ax25-ae350_64_defconfig as ae350_rv64_de
Hi Bin
Bin Meng 於 2018年12月18日 週二 上午10:50寫道：
>
> Hi Rick,
>
> On Tue, Dec 18, 2018 at 10:23 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > Bin Meng 於 2018年12月18日 週二 上午10:12寫道：
> > >
> > > Hi Rick,
> > >
> > > On Tu
arch/riscv/config.mk | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index
> 219e66683d..f7a2ffbbc6 100644
> --- a/arch/riscv/config.mk
> +++ b/arch/riscv/config.mk
> @@ -10,10 +10,6 @@
> # Rick Chen, Andes Technolo
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Thursday, August 30, 2018 3:54 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Subject: [PATCH 00/12] riscv: Add QEMU virt board support
>
> This series adds QEMU RISC-V 'virt' board target support, with the hope of
> helping peopl
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Thursday, August 30, 2018 3:54 PM
> To: Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List
> Subject: [PATCH 03/12] riscv: bootm: Correct the 1st kernel
argument to hart id
>
> The first argument of Linux kernel is the risc-v core hart id, from
w
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Tuesday, September 04, 2018 3:24 AM
> To: Bin Meng
> Cc: U-Boot Mailing List; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [PATCH] travis: Use kernel.org pre-built toolchain for riscv
>
> On Mon, Sep 03, 2018 at 05:50:39PM +0800, Bin Meng wrote:
> > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Wednesday, September 05, 2018 5:53 AM
> > To: bmeng...@gmail.com
> > Cc: Rick Jian-Zhi Chen(陳建志); u-boot@lists.denx.de
> > Subject: Re: [U-Boot] [PATCH 12/12] riscv: Add QEMU virt board support
> >
> > On Tue, 2018-09-04
Rick Chen 於 2018年9月5日 週三 上午9:28寫道：
>
> > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Wednesday, September 05, 2018 5:53 AM
> > > To: bmeng...@gmail.com
> > > Cc: Rick Jian-Zhi Chen(陳建志); u-boot@lists.denx.de
> > >
Bin Meng 於 2018年9月5日 週三 上午10:34寫道：
>
> Hi Rick,
>
> On Wed, Sep 5, 2018 at 9:27 AM Rick Chen wrote:
> >
> > > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > > > Sent: Wednesday, September 05, 2018 5:53 AM
> > > > To: bmen
Bin Meng 於 2018年9月6日 週四 上午9:43寫道：
>
> Hi Rick,
>
> On Tue, Sep 4, 2018 at 4:56 PM Bin Meng wrote:
> >
> > Hi Rick,
> >
> > On Tue, Sep 4, 2018 at 1:36 PM Rick Chen wrote:
> > >
> > > > From: Tom Rini [mailto:tr...@konsulko.com]
>
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Wednesday, June 06, 2018 1:21 AM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志)
> Subject: [PATCH] riscv: Add support for HI20 PE relocations
>
> The PE standard allows for HI20/LOW12 relocations. Within th
2018-06-06 17:18 GMT+08:00 Alexander Graf :
>
>
> On 06.06.18 11:15, Rick Chen wrote:
>>> -Original Message-
>>> From: Alexander Graf [mailto:ag...@suse.de]
>>> Sent: Wednesday, June 06, 2018 1:21 AM
>>> To: u-boot@lists.denx.de
>>>
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Wednesday, June 06, 2018 1:21 AM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志)
> Subject: [PATCH] ax25: Remove CONFIG_BOOTP_SERVERIP
>
> The config variable CONFIG_BOOTP_SERVERIP indicates on DHCP-TFTP fetches
> that the serverip vari
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Wednesday, June 06, 2018 8:32 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Joe Hershberger; Simon Glass
> Subject: [PATCH 1/2] net: Add option to prefer bootp/dhcp serverip
>
> Currently we can choose between 2 different types of
2018-05-28 14:45 GMT+08:00 Rick Chen :
> 2018-05-14 19:16 GMT+08:00 Tom Rini :
>> On Mon, May 14, 2018 at 04:31:27PM +0800, Rick Chen wrote:
>>> >> > > > > Related, is there a QEMU target for nds32 that we could leverage
>>> >> > > >
2018-06-13 3:59 GMT+08:00 Joe Hershberger :
> On Wed, Jun 6, 2018 at 8:54 PM, Rick Chen wrote:
>>> From: Alexander Graf [mailto:ag...@suse.de]
>>> Sent: Wednesday, June 06, 2018 8:32 PM
>>> To: u-boot@lists.denx.de
>>> Cc: Rick Jian-Zhi Chen(陳建志); Joe Hersh
2018-06-13 9:42 GMT+08:00 Rick Chen :
> 2018-06-13 3:59 GMT+08:00 Joe Hershberger :
>> On Wed, Jun 6, 2018 at 8:54 PM, Rick Chen wrote:
>>>> From: Alexander Graf [mailto:ag...@suse.de]
>>>> Sent: Wednesday, June 06, 2018 8:32 PM
>>>> To: u-boot@lists.
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, June 14, 2018 6:04 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Joe Hershberger; Greentime Ying-Han Hu(胡英
> 漢); Simon Glass
> Subject: [PATCH v2 0/3] net: Sanitize DHCP variable override
>
> While trying to boot from ne
serverip environment variable.
>>
>> Instead, let's use the new CONFIG_BOOT_PREFER_SERVERIP option to fall back
>> to the DHCP provided TFTP IP if no serverip environment variable is set.
>>
>> Signed-off-by: Alexander G
y: Neil Armstrong
> > Acked-by: Stefan Roese
> > Reviewed-by: Simon Goldschmidt
> > ---
for nds32 and riscv
> > arch/nds32/dts/ae3xx.dts | 2 +-
> > arch/riscv/dts/ae350_32.dts | 2 +-
> > arch/riscv/dts/ae350_64.dts | 2 +-
Reviewed-by: Rick Chen
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s = <3 4>;
> > flash@0 {
> > - compatible = "spi-flash";
> > + compatible = "jedec,spi-nor";
> > spi-max-frequency = <5000>;
> > reg =
Hi Lukas
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Monday, December 31, 2018 2:28 AM
> > To: u-boot@lists.denx.de
> > Cc: Anup Patel; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Bin Meng; Greentime Hu
> > Subject: [PATCH 2/6] riscv: remove invalid dcache flush implementation
Hi Lukas
Auer, Lukas 於 2019年1月2日 週三 下午8:22寫道：
>
> Hi Rick,
>
> On Wed, 2019-01-02 at 10:54 +0800, Rick Chen wrote:
> > Hi Lukas
> >
> > > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > > Sent: Monday, December 31, 2018 2:28 AM
&
Hi Lukas
Auer, Lukas 於 2019年1月4日 週五 上午8:40寫道：
>
> Hi Rick,
>
> On Thu, 2019-01-03 at 08:48 +0800, Rick Chen wrote:
> > Hi Lukas
> >
> > Auer, Lukas 於 2019年1月2日 週三 下午8:22寫道：
> > > Hi Rick,
> > >
> > > On Wed, 2019-01-02 at 10:54 +0800, R
igned long start, unsigned long end)
> > +
> > +__weak void flush_dcache_range(unsigned long start, unsigned long end)
> > {
> > - flush_dcache_all();
> > }
> >
> > void invalidate_icache_range(unsigned long start, unsigned long end) @@
> > -29,9
> > +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long
> > end)
> > invalidate_icache_all();
> > }
> >
> > -void invalidate_dcache_range(unsigned long start, unsigned long end)
> > +__weak void invalidate_dcache_range(unsigned long start, unsigned long
> > +end)
> > {
> > - flush_dcache_all();
> > }
> >
> > void cache_flush(void)
> > --
Reviewed-by: Rick Chen
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@@ -40,8 +40,8 @@ void cache_flush(void)
> >
> > void flush_cache(unsigned long addr, unsigned long size) {
> > - invalidate_icache_all();
> > - flush_dcache_all();
> > + invalidate_icache_range(addr, addr + size);
> > + flush_dcache_range(addr, addr + size);
> > }
> >
> > __weak void icache_enable(void)
> > --
Reviewed-by: Rick Chen
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Bin Meng 於 2018年10月8日 週一 下午1:49寫道：
>
> Hi Rick,
>
> On Mon, Oct 8, 2018 at 1:33 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > Use same dts to boot U-Boot and Kernel.
> >
> > Following are the change notes :
> > 1 Remove early printk boota
Bin Meng 於 2018年10月8日 週一 下午11:51寫道：
>
> Hi Rick,
>
> On Mon, Oct 8, 2018 at 1:36 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > Separate ax25-ae350 from one to two for
> > 32 and 64 bit individually. And also select
> > different dts for 32 and
Bin Meng 於 2018年10月8日 週一 下午11:48寫道：
>
> Hi Rick,
>
> On Mon, Oct 8, 2018 at 1:37 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > Add ae350_32.dts for 32 bit. And also rename
> > ae350.dts to ae350_64.dts for 64 bit.
> >
> > Signed-off-by: Ri
Bin Meng 於 2018年10月16日 週二 上午9:43寫道：
>
> Hi Rick,
>
> On Tue, Oct 16, 2018 at 9:25 AM Rick Chen wrote:
> >
> > Bin Meng 於 2018年10月8日 週一 下午1:49寫道：
> > >
> > > Hi Rick,
> > >
> > > On Mon, Oct 8, 2018 at 1:33 PM Andes wrote:
> > &
> From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> Sent: Saturday, October 20, 2018 6:08 AM
> To: u-boot@lists.denx.de
> Cc: Bin Meng; Lukas Auer; Greentime Hu; Alexander Graf; Rick Jian-Zhi
> Chen(陳建志)
> Subject: [PATCH 18/30] riscv: invalidate the instruction cache before jumping
> to
e tools/prelink-riscv.
>
> Signed-off-by: Lukas Auer
> ---
Reviewed-by: Rick Chen
>
> tools/.gitignore | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tools/.gitignore b/tools/.gitignore index c8cdaef90c..e5ede22842
> 100644
> --- a/tools/.gitignore
> +++
; +../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts
> +../arch/riscv/dts
Reviewed-by: Rick Chen
> --
> 2.17.2
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> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Monday, October 22, 2018 2:16 PM
> To: Lukas Auer
> Cc: U-Boot Mailing List; Rick Jian-Zhi Chen(陳建志)
> Subject: Re: [PATCH 02/30] riscv: ignore device tree binaries
>
> Hi Lukas,
>
> On Sat, Oct 20, 2018 at 6:08 AM Lukas Auer
> wrote:
> >
> > I
2 +-
> > > configs/ax25-ae350_defconfig| 2 +-
> > > configs/qemu-riscv64_defconfig | 2 +-
> > > include/config_distro_bootcmd.h | 8
> > > 5 files changed, 15 insertions(+), 15 deletions(-)
> > >
> >
> > > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
> > > Regards,
> > > Bin
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+
> > > 1 file changed, 1 insertion(+)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
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kas Auer
> > > ---
> > >
> > > arch/riscv/config.mk | 3 ++-
> > > 1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
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> > Subject: Re: [PATCH 09/30] riscv: move target selection into separate file
> >
> > Hi Lukas,
> >
> > On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
> > wrote:
> > >
> > > Move the target selection into a separate file (Kconfig.board) to
> > > avoid clutter once we support more boards.
> > >
> > >
> > -static void _exit_trap(int code, uint epc, struct pt_regs *regs)
> > +static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
> > {
> > static const char * const exception_code[] = {
> > "Instruction address misaligned",
> > @@ -70,6 +70,6 @@ static void _e
+
> > > arch/riscv/include/asm/io.h | 11 ++
> > > 2 files changed, 71 insertions(+), 7 deletions(-) create mode 100644
> > > arch/riscv/include/asm/barrier.h
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
> >
> > Regards,
> > Bin
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on and include the
> > > generic io.h instead.
> > >
> > > Signed-off-by: Lukas Auer
> > > ---
> > >
> > > arch/riscv/include/asm/io.h | 31 +++----
> > > 1 file changed, 3 insertions(+), 28 deletions(-)
>
t; arch/riscv/lib/interrupts.c | 13 -
> > > 1 file changed, 12 insertions(+), 1 deletion(-)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
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> arch/riscv/lib/interrupts.c | 8 ++--
> > > 1 file changed, 6 insertions(+), 2 deletions(-)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
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> > > Hang on unhandled exceptions to prevent execution in a faulty state.
> > >
> > > Signed-off-by: Lukas Auer
> > > ---
> > >
> > > arch/riscv/lib/interrupts.c | 2 ++
> > > 1 file changed, 2 insertions(
; > ---
> > >
> > > arch/riscv/lib/cache.c | 10 ++
> > > 1 file changed, 10 insertions(+)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
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v/cpu/start.S | 322
> > > -
> > > 1 file changed, 161 insertions(+), 161 deletions(-)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
> >
> > Regards,
> > Bin
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於 2018年10月23日 週二 下午4:41寫道：
>
> > Hi Lukas,
> >
> > On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
> > wrote:
> > >
> > > The machine trap-vector base address (mtvec) must be aligned on a
> > > 4-byte boundary. Add the necessary align directive to trap_entry.
> > >
> >
> > I don't think this explicit
owing commit :
commit d58717e42559189a226ea800173147399c8edef9
Author: Rick Chen
Date: Thu Mar 29 10:08:33 2018 +0800
riscv: ae250: Support DT provided by the board at runtime
B.R
Rick
> > >
> > > Signed-off-by: Lukas Auer
> > > ---
> > >
> > &g
Bin Meng 於 2018年10月24日 週三 上午11:34寫道：
>
> Hi Rich,
>
> On Wed, Oct 24, 2018 at 10:37 AM Rick Chen wrote:
> >
> > > > > The labels nmi_vector, trap_vector and handle_reset in start.S are not
> > > > > used for RISC-V. Remove them.
> > &g
Rick Chen 於 2018年10月24日 週三 下午1:20寫道：
>
> Bin Meng 於 2018年10月24日 週三 上午11:34寫道：
> >
> > Hi Rich,
> >
> > On Wed, Oct 24, 2018 at 10:37 AM Rick Chen wrote:
> > >
> > > > > > The labels nmi_vector, trap_vector and handle_reset in start.S are
gt; >
> > > Signed-off-by: Lukas Auer
> > > ---
> > >
> > > arch/riscv/cpu/start.S | 7 +++
> > > 1 file changed, 3 insertions(+), 4 deletions(-)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
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> > arch/riscv/cpu/start.S | 12 ++--
> > > 2 files changed, 16 insertions(+), 2 deletions(-)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
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emu-riscv64_defconfig | 2 +-
> > > 3 files changed, 2 insertions(+), 13 deletions(-)
> > >
> >
> > Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
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- Add a mem reserve
fdt rsvmem delete- Delete a mem reserves
fdt chosen [ ] - Add/update the /chosen branch in the tree
/ - initrd start/end addr
It seem that other arch (MICROBLAZE, ARM) also print fdt_blob in bdinfo cmd.
So I thin
Auer, Lukas 於 2018年10月24日 週三 下午10:14寫道：
>
> Hi Rick,
>
> On Wed, 2018-10-24 at 13:47 +0800, Rick Chen wrote:
> > Rick Chen 於 2018年10月24日 週三 下午1:20寫道：
> > >
> > > Bin Meng 於 2018年10月24日 週三 上午11:34寫道：
> > > >
> > > > Hi Rich
Bin Meng 於 2018年10月25日 週四 上午10:33寫道：
>
> Hi Rick,
>
> On Thu, Oct 25, 2018 at 9:20 AM Andes wrote:
> >
> > From: Rick Chen
> >
> > ax25-ae350 use CONFIG_OF_BOARD which allow the board to
> > override the fdt address. And prior_stage_fdt_address offer
Bin Meng 於 2018年10月25日 週四 上午11:16寫道：
>
> Hi Rick,
>
> On Thu, Oct 25, 2018 at 11:11 AM Rick Chen wrote:
> >
> > Bin Meng 於 2018年10月25日 週四 上午10:33寫道：
> > >
> > > Hi Rick,
> > >
> > > On Thu, Oct 25, 2018 at 9:20 AM Andes wrote:
>
Rick Chen 於 2018年10月16日 週二 上午10:01寫道：
>
> Bin Meng 於 2018年10月8日 週一 下午11:48寫道：
> >
> > Hi Rick,
> >
> > On Mon, Oct 8, 2018 at 1:37 PM Andes wrote:
> > >
> > > From: Rick Chen
> > >
> > > Add ae350_32.dts for 32 bit. And also ren
Auer, Lukas 於 2018年10月27日 週六 上午12:27寫道：
>
> Hi Rick,
>
> On Mon, 2018-10-22 at 09:39 +0800, Rick Chen wrote:
> > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Saturday, October 20, 2018 6:08 AM
> > > To: u-boot@lists.denx.de
>
Auer, Lukas 於 2018年10月27日 週六 上午12:32寫道：
>
> Hi Rick,
>
> On Mon, 2018-10-22 at 16:16 +0800, Andes wrote:
> > From: Rick Chen
> >
> > AndeStar V5 provide mcache_ctl register which can configure
> > I/D cache as enabled or disabled.
> >
> > This C
Bin Meng 於 2018年10月25日 週四 下午9:36寫道：
>
> Hi Rick,
>
> On Thu, Oct 25, 2018 at 11:27 AM Rick Chen wrote:
> >
> > Bin Meng 於 2018年10月25日 週四 上午11:16寫道：
> > >
> > > Hi Rick,
> > >
> > > On Thu, Oct 25, 2018 at 11:11 AM Rick Chen
ctions or can I apply this to u-boot-mips/next? Thanks.
> >
> > Go ahead:
> >
> > Reviewed-by: Tom Rini
> >
Reviewed-by: Rick Chen
> > --
> > Tom
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Auer, Lukas 於 2018年10月30日 週二 上午12:43寫道：
>
> Hi Rick,
>
> On Thu, 2018-10-25 at 15:56 +, Auer, Lukas wrote:
> > Hi Rick,
> >
> > On Thu, 2018-10-25 at 09:16 +0800, Rick Chen wrote:
> > > Auer, Lukas 於 2018年10月24日 週三
> > > 下午10:14寫道：
> > &
Auer, Lukas 於 2018年10月29日 週一 下午8:13寫道：
>
> Hi Rick,
>
> On Mon, 2018-10-29 at 11:16 +0800, Rick Chen wrote:
> > Auer, Lukas 於 2018年10月27日 週六
> > 上午12:32寫道：
> > >
> > > Hi Rick,
> > >
> > > On Mon, 2018-10-22 at 16:16 +0800, Andes
Greentime Hu 於 2018年10月31日 週三 上午11:48寫道：
>
> Rick Chen 於 2018年10月29日 週一 上午10:25寫道：
> >
> > Auer, Lukas 於 2018年10月27日 週六 上午12:27寫道：
> > >
> > > Hi Rick,
> > >
> > > On Mon, 2018-10-22 at 09:39 +0800, Rick Chen wrote:
> > &
於 2018年11月1日 週四 下午12:13寫道：
>
> > RISC-V does not guarantee that stores to instruction memory are visible to
> > instruction fetches (i.e. incoherent instruction caches). Invalidate the
> > instruction
> > cache to ensure the kernel function pointer points to the correct memory
> > location.
> >
>
Auer, Lukas 於 2018年11月4日 週日 下午10:21寫道：
>
> Hi Rick,
>
> On Thu, 2018-11-01 at 12:08 +0800, Andes wrote:
> > From: Rick Chen
> >
> > AndeStar RISC-V(V5) provide mcache_ctl register which
> > can configure I/D cache as enabled or disabled.
> >
> > T
Hi Bin
Bin Meng 於 2018年11月4日 週日 下午10:31寫道：
>
> Hi Rick,
>
> On Thu, Nov 1, 2018 at 12:10 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > AndeStar RISC-V(V5) provide mcache_ctl register which
> > can configure I/D cache as enabled or disabled
> > > Drop the _AC and UL macros from common.h. Linux headers is the
> > > original source of this macro, so keep its definition in the same header.
> > >
> > > Update existing users of these macros to include const.h directly.
> > >
> > > Cc:
> > This patch series includes general fixes and cleanup for RISC-V. It also
> > adds
> > support for booting Linux on qemu-riscv. At the moment, only single-core
> > systems are supported. Support for multi-core systems will be added with a
> > future patch series.
> >
> > To boot Linux on qemu-r
Bin Meng 於 2018年11月13日 週二 下午2:49寫道：
>
> Hi Rick,
>
> On Tue, Nov 13, 2018 at 2:41 PM Rick Chen wrote:
> >
> > > > This patch series includes general fixes and cleanup for RISC-V. It
> > > > also adds
> > > > support for bootin
於 2018年11月14日 週三 下午3:35寫道：
>
> > Hi Lukas,
> >
> > On Tue, Nov 13, 2018 at 10:45 PM Auer, Lukas
> >
> > wrote:
> > >
> > > Hi Bin,
> > >
> > > On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> > > > This adds U-Boot syscon driver for RISC-V Core Local Interruptor
> > > > (CLINT). The CLINT bl
Auer, Lukas 於 2018年11月17日 週六 上午6:01寫道：
>
> Hi Rick,
>
> On Tue, 2018-11-13 at 14:52 +0800, Rick Chen wrote:
> > Bin Meng 於 2018年11月13日 週二 下午2:49寫道：
> > >
> > > Hi Rick,
> > >
> > > On Tue, Nov 13, 2018 at 2:41 PM Rick Chen
> > >
> >
> > Do any of your above patches get v2 posted? At least I did not see any
> > follow-up
> > response [1] regarding to "riscv: ax25-ae350: Pass dtb address to u-boot
> > with a1
> > register"
First of all you told me about that
board_fdt_blob_setup() should be completely removed.
Instead the
Bin Meng 於 2018年11月21日 週三 下午3:18寫道：
>
> Hi Rick,
>
> On Wed, Nov 21, 2018 at 2:00 PM Rick Chen wrote:
> >
> > > >
> > > > Do any of your above patches get v2 posted? At least I did not see any
> > > > follow-up
> > > > response [
Rick Chen 於 2018年11月21日 週三 下午4:53寫道：
>
> Bin Meng 於 2018年11月21日 週三 下午3:18寫道：
> >
> > Hi Rick,
> >
> > On Wed, Nov 21, 2018 at 2:00 PM Rick Chen wrote:
> > >
> > > > >
> > > > > Do any of your above patches get v2 posted?
Hi Lukas
> >
> > Hi Rick,
> >
> > Thanks for pulling my changes! I have some notes and questions on it.
> >
> > I can't find all of your patches on the mailing list, for example the patch
> > "configs:
> > ax25-ae350: Enable DISPLAY_CPUINFO & DISPLAY_BOARDINFO". Others include
> > changes, which
Auer, Lukas 於 2018年11月21日 週三 下午9:09寫道：
>
> Hi Rick,
>
> On Wed, 2018-11-21 at 17:37 +0800, Rick Chen wrote:
> > Hi Lukas
> >
> > > >
> > > > Hi Rick,
> > > >
> > > > Thanks for pulling my changes! I have some notes and ques
Auer, Lukas 於 2018年11月22日 週四 下午5:18寫道：
>
> Hi Rick,
>
> On Thu, 2018-11-22 at 16:38 +0800, Rick Chen wrote:
> > Auer, Lukas 於 2018年11月21日 週三
> > 下午9:09寫道：
> > >
> > > Hi Rick,
> > >
> > > On Wed, 2018-11-21 at 17:37 +0800, Rick Chen wro
-T $(srctree)/examples/standalone/riscv.lds
>
> PLATFORM_CPPFLAGS+= -ffixed-gp -fpic
> -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2
> -ffunction-sections
> +PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections
> LDFLAGS_u-boot += --gc-sec
> Hi Rick,
>
> On Tue, Sep 11, 2018 at 12:50 PM Bin Meng wrote:
> >
> > This series adds QEMU RISC-V 'virt' board target support, with the
> > hope of helping people easily test U-Boot on RISC-V.
> >
> > Some existing RISC-V codes have been changed to make it easily to
> > support new tar
Choose this option to build an U-Boot for RISCV32 architecture.
>
> config CPU_RISCV_64
> - bool "RISCV 64 bit"
> + bool "RISC-V 64-bit"
> select 64BIT
> help
> Choose this option to build an U-Boot for RISCV64 architecture.
> --
> 2.7.4
Reviewed-by: Rick Chen
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bootm_headers_t *images)
> printf("\nStarting kernel ...\n\n");
>
> cleanup_before_linux();
> + /* TODO: hardcode the hart id to zero for now */
> if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
> - theKernel(machid, (unsigned long)images->ft_addr);
> + kernel(0, images->ft_addr);
>
> /* does not return */
>
Reviewed-by: Rick Chen
> --
> 2.7.4
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-#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
> -typeof(_bit) (bit) = (_bit); \
> -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
> - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
> -else \
> - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
> - __tmp; })
> -
> -#define rdtime() read_csr(time)
> -#define rdcycle() read_csr(cycle)
> -#define rdinstret() read_csr(instret)
> +#endif /* __riscv */
>
> -#endif
> -#endif
> -#endif
> -#endif
> +#endif /* RISCV_CSR_ENCODING_H */
Reviewed-by: Rick Chen
> --
> 2.7.4
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inux();
> - /* TODO: hardcode the hart id to zero for now */
> +
> if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
> - kernel(0, images->ft_addr);
> + kernel(csr_read(mhartid), images->ft_addr);
>
> /* does not return */
>
Reviewed-by: Rick Chen
> > --
> 2.7.4
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+= reset.o
> obj-y += setjmp.o
>
> # For building EFI apps
> diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c new
file mode 100644
> index 000..5d9b99c
> --- /dev/null
> +++ b/arch/riscv/lib/reset.c
> @@ -0,0 +1,14 @@
> +//
> > > Hi Rick,
> > >
> > > On Wed, Sep 26, 2018 at 9:50 PM Bin Meng wrote:
> > > >
> > > > This series adds QEMU RISC-V 'virt' board target support, with the
> > > > hope of helping people easily test U-Boot on RISC-V.
> > > >
> > > > Some existing RISC-V codes have been changed to make it easily
Heinrich Schuchardt 於 2018年9月24日 週一 上午4:06寫道：
>
> On 08/07/2018 10:57 AM, Rick Chen wrote:
> >> If environment variable CROSS_COMPILE is not set, this indicates native
> >> compilation. In this case we should not set an arbitrary value which is not
> >
Tom Rini 於 2018年10月3日 週三 上午9:23寫道：
>
> On Wed, Oct 03, 2018 at 09:16:48AM +0800, Rick Chen wrote:
> > Heinrich Schuchardt 於 2018年9月24日 週一 上午4:06寫道：
> > >
> > > On 08/07/2018 10:57 AM, Rick Chen wrote:
> > > >> If environment variable CR
ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.
Signed-off-by: rick
Signed-off-by: Rick Chen
Reviewed-by: Simon Glass
---
configs/adp-ae3xx_defconfig | 2 +-
drivers/timer/Kconfig | 7
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