> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de] > > Sent: Friday, January 04, 2019 8:38 AM > > To: u-boot@lists.denx.de > > Cc: Anup Patel; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Bin Meng; Greentime Hu > > Subject: [PATCH v2 3/7] riscv: use invalidate/flush_*cache_range functions > > in > > cache.c > > > > The flush_cache() function in lib/cache.c ignores its arguments and flushes > > the > > complete data and instruction caches. Use the > > invalidate/flush_*cache_range() functions instead to only flush the > > requested > > memory region. > > > > This patch does not change the current behavior of U-Boot, since the > > implementation of the invalidate/flush_*cache_range() functions flush the > > complete data and instruction caches. It is in preparation for CPUs with the > > necessary functionality for flushing a selectable memory range. > > > > Signed-off-by: Lukas Auer <lukas.a...@aisec.fraunhofer.de> > > --- > > > > Changes in v2: > > - New patch "riscv: use invalidate/flush_*cache_range functions in cache.c" > > > > arch/riscv/lib/cache.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index > > 78b19da2c5..5437a122a1 100644 > > --- a/arch/riscv/lib/cache.c > > +++ b/arch/riscv/lib/cache.c > > @@ -40,8 +40,8 @@ void cache_flush(void) > > > > void flush_cache(unsigned long addr, unsigned long size) { > > - invalidate_icache_all(); > > - flush_dcache_all(); > > + invalidate_icache_range(addr, addr + size); > > + flush_dcache_range(addr, addr + size); > > } > > > > __weak void icache_enable(void) > > --
Reviewed-by: Rick Chen <r...@andestech.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
