On 2023-10-13 03:40, Chris Packham wrote:
Hi Marc, Paul,
On Sat, Mar 18, 2023 at 5:23 AM Ying-Chun Liu (PaulLiu)
wrote:
From: Marc Zyngier
Some recent arm64 cores have a facility that allows the page
table walker to track the dirty state of a page. This makes it
really efficient to perform
On Mon, 16 Oct 2023 02:42:08 +0100,
Chris Packham wrote:
>
> On Sun, Oct 15, 2023 at 10:29 AM Chris Packham
> wrote:
> >
> >
> >
> > On Sat, 14 Oct 2023, 11:04 am Marc Zyngier, wrote:
> >>
> >> On 2023-10-13 03:40, Chris Packham wrote:
>
On 2023-10-18 21:53, Chris Packham wrote:
Since commit 6cdf6b7a340d ("arm64: Use FEAT_HAFDBS to track dirty pages
when available") the default get_page_table_size() sets some flags for
more efficient handling of dirty page table entries. This causes
problems on the AC5/AC5X SoC (specifically a lo
Hi Pierre-Clément,
On Fri, 27 Oct 2023 10:49:47 +0100,
Pierre-Clément Tosi wrote:
>
> Hi Chris,
>
> On Fri, Oct 27, 2023 at 01:23:51PM +1300, Chris Packham wrote:
> > As discussed this series reverts the HAFDBS changes that caused an issue
> > on AC5/AC5X. I think there are some improvements th
On Fri, 25 Aug 2023 19:05:32 +0100,
Sam Edwards wrote:
>
> On 8/25/23 00:20, Chen-Yu Tsai wrote:
>
> Hi Chen-Yu,
>
> > IIRC the GIC manual says that the secure bit is set or cleared to select
> > which bank of registers is accessed.
>
> Which secure bit are we talking about here? Do we mean th
On Tue, 01 Aug 2023 09:53:52 +0100,
Oliver Graute wrote:
>
> On 14/02/23, Ying-Chun Liu (PaulLiu) wrote:
> > From: Marc Zyngier
> >
> > In the add_map() function, for each level it populates, it iterates from
> > the root of the PT tree, making it ineficie
On Mon, 14 Aug 2023 21:39:10 +0100,
Andre Przywara wrote:
>
> On Wed, 31 May 2023 14:15:20 -0600
> Sam Edwards wrote:
>
> Hi,
>
> (CC:ing Marc and Chen-Yu as the original authors)
>
> sorry for the delay, found that mouldering in my Drafts folder.
>
> > The nonsec code overrides/handles thes
Hi Ivan,
On 2023-12-18 21:03, Ivan T. Ivanov wrote:
Hi,
These patches are adding basic support for RPi5.
They are based on v2 series from Dmitry Malkin[1].
With them I am able to _start_ current openSUSE
Tumbleweed without modification. They are still
a lot of things to be added to the upstrea
On 2023-12-22 12:33, Ivan T. Ivanov wrote:
On 12-22 12:19, Marc Zyngier wrote:
Hi Ivan,
On 2023-12-18 21:03, Ivan T. Ivanov wrote:
> Hi,
>
> These patches are adding basic support for RPi5.
> They are based on v2 series from Dmitry Malkin[1].
>
> With them I am able
[Fixing Ard's email address for something more current.]
On Sat, 10 Feb 2024 12:07:09 +,
Igor Opaniuk wrote:
>
> From: Igor Opaniuk
>
> Add support for the SHA-512 Secure Hash Algorithm which uses ARMv8 Crypto
> Extensions. The CPU should support ARMv8.2 instruction set and implement
> SHA
EL1 code to enable access to the FP/SIMD registers. This allows
U-Boot to run on systems that pass control to U-Boot in EL2 with
EL2 Host mode enabled such as machines using Apple's M1 SoC.
Signed-off-by: Mark Kettenis
---
v4: use EL1 codepath when HCR_EL2.E2H is set
suggested by Marc Zy
Hi Mark,
On 2021-02-11 10:22, Mark Kettenis wrote:
Date: Thu, 11 Feb 2021 09:58:49 +
From: Marc Zyngier
On 2021-02-10 19:14, Mark Kettenis wrote:
> On implementations that support VHE, the layout of the CPTR_EL2
> register depends on whether HCR_EL2.E2H is set. If the bit is
(host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
> >> - ctrl &= ~SDHCI_CTRL_HISPD;
> >> + if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
> >
> > Should that be "&&" rather than "||"? Otherwise this will always
> > evaluate to true unless *both* quirks are set, which isn't
> > equivalent to the check being removed above.
>
>
> You're right.
It'd be great if you could respin this patch quickly and get it merged,
as it just helped me getting my NanoPC-T4 up and running.
FWIW:
Tested-by: Marc Zyngier
M.
--
Jazz is not dead. It just smells funny...
can select
this option and perform by-VA cache maintenance instead of using the
set/way instructions.
Signed-off-by: Ying-Chun Liu (PaulLiu)
Signed-off-by: Marc Zyngier
Signed-off-by: Will Deacon
Cc: Tom Rini
The sign-off chain looks pretty odd. Either you are the author
of this patch, and I
On Tue, 07 Feb 2023 16:40:05 +,
Tom Rini wrote:
>
> On Tue, Feb 07, 2023 at 04:35:25PM +, Marc Zyngier wrote:
> > On 2023-02-07 16:20, Ying-Chun Liu (PaulLiu) wrote:
> > > Exposing set/way cache maintenance to a virtual machine is unsafe, not
> > > least be
On Tue, 07 Feb 2023 17:18:27 +,
Paul Liu wrote:
>
> Hi Marc,
>
> I think you are the author. I'm just making some minor fixes and
> then upstreaming to the mailing list. What is the correct way to
> make the Signed-off-by list?
In general, and unless you have completely rewritten the patch
On 2020-12-07 07:14, Priyanka Jain wrote:
From: Nikhil Gupta
Add programming of GIC LPI configuration table:
1. Program Redistributor PROCBASER configuration table
The register name is GICR_PROPBASER.
which is common for all redistributors.
2. Program Redistributor pending table (PENDBAS
Hi Ian,
On Sun, Dec 29 2013 at 07:07:56 PM, Ian Campbell wrote:
> Some users of the u-boot API (specifically grub) use the initial SP as a hint
> regarding where to look for the u-boot API signature.
That looks really fragile...
> Signed-off-by: Ian Campbell
> Cc: Marc Zyngier
IG_ARMV7_PSCI
> smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
> smp_kick_all_cpus();
> #endif
>
> /* call the non-sec switching code on this CPU also */
> - relocate_secure_section();
> secure_ram_addr(_nonsec_init)()
On 18/02/15 17:42, surya.satyav...@sirabtech.com wrote:
> I am trying to bring up xen suing u-boot that has this patch.
> Unfortunately as soon as the code tries to call _nonsec_init through
> secure_ram_addr in arm7_init_nonsec function in virt-v7.c I get an
> undefined instruction exception. I su
On 12/02/14 08:36, Albert ARIBAUD wrote:
> Hi Albert,
>
> On Thu, 12 Dec 2013 11:47:31 +0100, Albert ARIBAUD
> wrote:
>
>> Hi Marc,
>>
>> On Sat, 7 Dec 2013 11:19:12 +, Marc Zyngier
>> wrote:
>>
>>> The current non-sec switching c
Hi Albert,
On 13/02/14 10:11, Albert ARIBAUD wrote:
> Hi Marc,
>
> On Sat, 7 Dec 2013 11:19:05 +0000, Marc Zyngier
> wrote:
>
>> PSCI is an ARM standard that provides a generic interface that
>> supervisory software can use to manage power in the following
&g
CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...
Signed-off-by: Marc Zyngier
---
include/configs/sun7i.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/sun7i.h b
Move the B and D SRAM bank to their actual location (or at least
where the documentation pretends they are).
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/arch-sunxi/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b
Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.
Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.
Signed-off-by: Marc Zyngier
---
arch/arm/lib/b
From: Ma Haijun
Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.
[maz: collapsed 3 patches into one, rewrote commit message]
Signed-off-by: Ma Haijun
Signed-off-by: Marc Zyngier
---
arch
In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.
Nothing is using it just yet.
Signed-off-by: Marc Zyngier
---
arch/arm/config.mk | 2 +-
arch/arm/cpu/u-boot.lds | 30 ++
arch
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.
Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/proc-armv/ptrace.h | 2 ++
arch
quite primitive.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 161 +++
arch/arm/cpu/armv7/virt-v7.c | 59 +-
arch/arm/include/asm/armv7.h | 10 ++-
arch/arm/include/asm/secure.h| 26 +++
arch/arm/lib/bo
arch_fixup_memory_node to a generic FDT fixup function
Marc Zyngier (12):
ARM: HYP/non-sec: move switch to non-sec to the last boot phase
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
ARM: non-sec: reset CNTVOFF to zero
ARM: add missing HYP mode constant
ARM: HYP/non-sec: add se
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/Makefile | 4 ++
arch/arm/cpu/armv7/psci.S
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...
Signed-off-by: Marc Zyngier
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
Allow the switch to a second stage secure monitor just before
switching to non-secure.
This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7
Generate the PSCI node in the device tree.
Also add a reserve section for the "secure" code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/
So far, only supporting the CPU_ON method.
Other functions can be added later.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/sunxi/Makefile | 3 +
arch/arm/cpu/armv7/sunxi/psci.S | 162 ++
include/configs/sun7i.h | 6 ++
3 files changed
Hi Albert,
On 2014-02-15 14:45, Albert ARIBAUD wrote:
On Sat, 15 Feb 2014 13:36:24 +, Marc Zyngier
wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory software can use to manage power in the following
situations:
There seems to be no history information
Hi,
On 2014-02-25 13:38, Ezaul Zillmer wrote:
Hi Marc Zyngier
Where could obtain this repository with these alterations to be able
to
test
virtualization with KVM on my cubieboard2'm using Kernel 3.14.rc4
I appreciate if you help
You're looking at an older patch series. The new
Hi Siarhei,
On 03/08/14 03:36, Siarhei Siamashka wrote:
> Unlike 9d195a546179bc732aba9eacccf0a9a3db591288, which had removed
> the MIDR check against the "white list" of supported CPUs earlier,
> now we introduce the "black list" of unsupported CPUs.
>
> The current PSCI code is not compatible wi
On 06/08/14 10:49, Mark Rutland wrote:
> On Wed, Aug 06, 2014 at 08:38:13AM +0100, Ian Campbell wrote:
>> On Mon, 2014-08-04 at 16:14 +0100, Marc Zyngier wrote:
>>
>>> My personal feeling is that booting in secure mode is always the wrong
>>> thing to do.
>>
On 07/08/14 02:54, Xiubo Li wrote:
> The memory where loaded the smp_waitloop code section probablly
> be corrupted by Linux Kernel, then the secondary cores will be
> running the random code, leading booting the secondary cores
> failed.
There is now similar reservation code in virt-dt.c. Probabl
ifically for the
>> purpose.
>>
>> So far no one is using this section.
>>
>> Signed-off-by: Arnab Basu
>> Reviewed-by: Bhupesh Sharma
>> Cc: Marc Zyngier
>> ---
>> arch/arm/config.mk|2 +-
>> arch/arm/cpu/armv8/u-boot.lds |
On 2014-10-11 12:27, Albert ARIBAUD wrote:
Hi Albert,
On Fri, 19 Sep 2014 18:04:14 +0200, Albert ARIBAUD
wrote:
Hi Marc,
On Thu, 18 Sep 2014 16:28:52 +0100, Marc Zyngier
wrote:
> On Thu, Sep 18 2014 at 10:12:17 AM, Albert ARIBAUD
wrote:
> > Hi Arnab,
> >
> > On T
c (and hyp) support.
>
> Signed-off-by: Hans de Goede
Looks good to me.
Acked-by: Marc Zyngier
M.
--
Jazz is not dead. It just smells funny.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
On Wed, Oct 15 2014 at 11:25:10 AM, Siarhei Siamashka
wrote:
> On Wed, 15 Oct 2014 12:13:05 +0200
> Hans de Goede wrote:
>
>> Older Linux kernels will not properly boot in hype mode, add support for a
>> bootm_boot_mode environment variable, which when set to "sec" will cause
>> u-boot to boot i
On Wed, Oct 15 2014 at 11:25:43 AM, Albert ARIBAUD
wrote:
> Hi Marc, Hans,
>
> On Wed, 15 Oct 2014 11:18:28 +0100, Marc Zyngier
> wrote:
>
>> On Wed, Oct 15 2014 at 11:13:05 AM, Hans de Goede
>> wrote:
>> > Older Linux kernels will not properly
On Wed, Oct 15 2014 at 11:40:24 AM, Siarhei Siamashka
wrote:
> On Wed, 15 Oct 2014 11:31:44 +0100
> Marc Zyngier wrote:
>
>> On Wed, Oct 15 2014 at 11:25:10 AM, Siarhei Siamashka
>> wrote:
>> > On Wed, 15 Oct 2014 12:13:05 +0200
>> > Hans de Goede wro
On Wed, Oct 15 2014 at 03:05:24 PM, Siarhei Siamashka
wrote:
> On Wed, 15 Oct 2014 13:42:33 +0100
> Marc Zyngier wrote:
>
>> On Wed, Oct 15 2014 at 11:40:24 AM, Siarhei Siamashka
>> wrote:
>> > On Wed, 15 Oct 2014 11:31:44 +0100
>> > Marc Zyngier wrote:
On 23/05/13 11:52, Albert ARIBAUD wrote:
> Hi Andre,
>
> On Mon, 6 May 2013 15:17:45 +0200, Andre Przywara
> wrote:
>
>> A prerequisite for using virtualization is to be in HYP mode, which
>> requires the CPU to be in non-secure state.
>> Introduce a monitor handler routine which switches the C
Hi Liu,
On 30/05/14 03:25, tiger...@via-alliance.com wrote:
> Hi, Marc:
> I am studying ARMv8's u-boot code with FVP model.
> In do_nonsec_virt_switch() function in bootm.c :
> It will call smp_kick_all_cpus() function :
> It seems it would set GICD_SGIR[24] = 1, forward the interrupt to all
> CPU
On Tue, Jun 03 2014 at 3:16:19 am BST, "tiger...@via-alliance.com"
wrote:
> Hi， Marc:
>>In short, if you're setting GICD_SGIR[24] to 1, you're sending SGI0 to
>>all CPUs but yourself. This seems to match the name of the function,
>>doesn't it?
> I described my understanding based on 2014.07-RC2
On Tue, Jun 03 2014 at 10:41:51 am BST, "tiger...@via-alliance.com"
wrote:
> Hi, Marc:
>>My understanding is that if you're using the Trusted Firmware, then you
>>have an implementation of PSCI, and that's what you must use to bring
>>the CPUs into u-boot. U-Boot will be running non-secure anyway
On 08/06/14 08:57, Albert ARIBAUD wrote:
> On Sun, 25 May 2014 16:08:44 +0200, Albert ARIBAUD
> wrote:
>
>> Hi Marc,
>>
>> On Sat, 26 Apr 2014 13:17:01 +0100, Marc Zyngier
>> wrote:
>>
>>> PSCI is an ARM standard that provides a generic interface
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/Makefile | 4 ++
arch/arm/cpu/armv7/psci.S
Allow the switch to a second stage secure monitor just before
switching to non-secure.
This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7
PSCI doesn't need any pen-related code, as it interacts directly
with the power controller.
Make these sections depend on CONFIG_ARMV7_PSCI not being set.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 2 ++
arch/arm/cpu/armv7/virt-v7.c | 2 ++
2 files chang
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
So far, only supporting the CPU_ON method.
Other functions can be added later.
Signed-off-by: Marc Zyngier
---
Makefile | 5 ++
arch/arm/cpu/armv7/sunxi/Makefile| 3 +
arch/arm/cpu/armv7/sunxi/config.mk | 6 +-
arch/arm/cpu/armv7/sunxi/psci.S
scribed to. Please keep me on Cc for any comment you may have.
Cheers,
M.
Marc Zyngier (9):
ARM: HYP/non-sec: fix alignment requirements for vectors
ARM: HYP/non-sec: move switch to non-sec to the last boot phase
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
ARM: non-
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...
Signed-off-by: Marc Zyngier
Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.
Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.
Signed-off-by: Marc Zyngier
---
arch/arm/lib/b
CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...
Signed-off-by: Marc Zyngier
---
include/configs/sun7i.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/sun7i.h b
Make sure the vectors are aligned on a 32 byte boundary, not
the code that deals with it...
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
Hi Masahiro,
On 21/11/13 10:19, Masahiro Yamada wrote:
> Hello Marc
>
>> +.align 5 @ Minimal alignment for vectors
>> +
>> /* the vector table for secure state and HYP mode */
>> _monitor_vectors:
>> .word 0 /* reset */
>> @@ -32,7 +34,6 @@ _monitor_vecto
Hi Rob,
On 21/11/13 14:28, Rob Herring wrote:
> On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier wrote:
>> PSCI is an ARM standard that provides a generic interface that
>> supervisory software can use to manage power in the following
>> situations:
>> - Core idle
On 22/11/13 03:58, Anup Patel wrote:
> On 22 November 2013 07:24, Christoffer Dall
> wrote:
>> On 21 November 2013 07:04, Marc Zyngier wrote:
>>> Hi Rob,
>>>
>>> On 21/11/13 14:28, Rob Herring wrote:
>>>> On Thu, Nov 21, 2013 at 2:59 AM, Marc
On 22/11/13 01:54, Christoffer Dall wrote:
> On 21 November 2013 07:04, Marc Zyngier wrote:
>> Hi Rob,
>>
>> On 21/11/13 14:28, Rob Herring wrote:
>>> On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier wrote:
>>>> PSCI is an ARM standard that provides
On 22/11/13 01:51, Christoffer Dall wrote:
> On 21 November 2013 00:59, Marc Zyngier wrote:
>> A CP15 instruction execution can be reordered, requiring an
>> isb to be sure it is executed in program order.
>>
>> Signed-off-by: Marc Zyngier
>> ---
>> arch/
On 22/11/13 08:40, Ian Campbell wrote:
> On Thu, 2013-11-21 at 15:04 +0000, Marc Zyngier wrote:
>> Hi Rob,
>>
>> On 21/11/13 14:28, Rob Herring wrote:
>>> On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier wrote:
>>>> PSCI is an ARM standard that provides
On 26/11/13 14:41, Andre Przywara wrote:
> On 11/21/2013 09:59 AM, Marc Zyngier wrote:
>> Before switching to non-secure, make sure that CNTVOFF is set
>> to zero on all CPUs. Otherwise, kernel running in non-secure
>> without HYP enabled (hence using virtual timers) may obser
Hi Andre,
On 06/12/13 11:43, Andre Przywara wrote:
> On 11/21/2013 09:59 AM, Marc Zyngier wrote:
>> PSCI is an ARM standard that provides a generic interface that
>> ...
>
> Thanks again for posting this, I like the idea of adding PSCI handlers
> to u-boot for sev
On 06/12/13 13:03, Andre Przywara wrote:
> Yes, there is indeed this problem with the pen. Maybe one can use your
> upcoming relocation code to move the pen to a more secure place (defined
> per platform).
Yes, that's what I've done. Also rewritten some of it to be able to
execute solely in sec
2013-12-06 at 12:59 +, Ian Campbell wrote:
>>>> On Fri, 2013-12-06 at 12:12 +, Marc Zyngier wrote:
>>>>>> BTW: Yesterday my PSCI host patches for Xen have been committed, so Xen
>>>>>> should be able to use that feature just like the kernel does.
>
In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.
Nothing is using it just yet.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/u-boot.lds | 30 ++
arch/arm/lib/sections.c | 2 ++
2
o lists I'm not
subscribed to. Please keep me on Cc for any comment you may have.
Cheers,
M.
Marc Zyngier (13):
ARM: HYP/non-sec: fix alignment requirements for vectors
ARM: HYP/non-sec: move switch to non-sec to the last boot phase
ARM: HYP/non-sec: add a barrier after setting
Allow the switch to a second stage secure monitor just before
switching to non-secure.
This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...
Signed-off-by: Marc Zyngier
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.
Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/proc-armv/ptrace.h | 2 ++
arch
Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.
Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.
Signed-off-by: Marc Zyngier
---
arch/arm/lib/b
Make sure the vectors are aligned on a 32 byte boundary, not
the code that deals with it...
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/Makefile | 4 ++
arch/arm/cpu/armv7/psci.S
quite primitive.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 161 +++
arch/arm/cpu/armv7/virt-v7.c | 59 +-
arch/arm/include/asm/armv7.h | 10 ++-
arch/arm/include/asm/secure.h| 26 +++
arch/arm/lib/bo
Move the B and D SRAM bank to their actual location (or at least
where the documentation pretends they are).
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/arch-sunxi/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b
CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...
Signed-off-by: Marc Zyngier
---
include/configs/sun7i.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/sun7i.h b
So far, only supporting the CPU_ON method.
Other functions can be added later.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/sunxi/Makefile| 3 +
arch/arm/cpu/armv7/sunxi/psci.S | 124 +++
arch/arm/cpu/armv7/sunxi/u-boot-psci.lds | 63
Commit b3a7f22b3e09 (ARM: vexpress: convert to common timer code)
converted the VE timer code to the generic framework, but hardcoded
the timer address of the A9 testchip.
Change it for the appropriate macro that works on both core tiles.
Signed-off-by: Marc Zyngier
---
include/configs
Generate the PSCI node in the device tree.
Also add a reserve section for the "secure" code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/
On 07/12/13 21:03, Rob Herring wrote:
> On Sat, Dec 7, 2013 at 5:11 AM, Marc Zyngier wrote:
>> Commit b3a7f22b3e09 (ARM: vexpress: convert to common timer code)
>> converted the VE timer code to the generic framework, but hardcoded
>> the timer address of the A9 testchip.
&g
On 09/12/13 10:51, Ian Campbell wrote:
> On Sat, 2013-12-07 at 11:19 +0000, Marc Zyngier wrote:
>> The kernel now boots in HYP mode, finds its secondary CPU without any
>> SMP code present in the kernel, and runs KVM out of the box.
>> Hopefully, the Xen/ARM guys can do t
On 09/12/13 11:29, Hans de Goede wrote:
> Hi,
>
> On 12/09/2013 11:51 AM, Ian Campbell wrote:
>> On Sat, 2013-12-07 at 11:19 +0000, Marc Zyngier wrote:
>>> The kernel now boots in HYP mode, finds its secondary CPU without any
>>> SMP code present in the ke
On 2013-07-30 18:07, Alexander Spyridakis wrote:
Hi Alexander,
Since there was much interest, as of late, to see KVM/ARM running on
Samsung's Exynos5250 Chromebook, and given the fact that we are not
aware
of any current work done on this, we take the opportunity to inform
you
that you can t
On 16/04/14 15:45, Albert ARIBAUD wrote:
> Hi Marc,
>
> On Sat, 15 Feb 2014 13:36:24 +0000, Marc Zyngier
> wrote:
>
>> PSCI is an ARM standard that provides a generic interface that
>> supervisory software can use to manage power in the following
>> situ
On Thu, Apr 17 2014 at 9:34:24 am BST, Albert ARIBAUD
wrote:
> Hi Marc,
>
> On Wed, 16 Apr 2014 17:09:07 +0100, Marc Zyngier
> wrote:
>
>> On 16/04/14 15:45, Albert ARIBAUD wrote:
>> > Hi Marc,
>> >
>> > On Sat, 15 Feb 2014 13:36:24 +, Marc
On Thu, Apr 17 2014 at 08:55:56 PM, Jon Loeliger wrote:
>> No, so far there hasn't been much discussion, and people seem happy with
>> it. I have a couple of fixes lined up, but nothing major.
>
> So, I think PSCI 0.2 calls for function numbers in the 0x8400 range.
> Seems like we'll have to f
On Thu, Apr 17 2014 at 09:01:07 PM, Jon Loeliger wrote:
> [ Drat. I meant to send this to the U-Boot list, not just Albert. --jdl]
>
> -- Forwarded message --
> From: Jon Loeliger
> Date: Thu, Apr 17, 2014 at 11:36 AM
> Subject: Re: [U-Boot] [PATCH v3 00/13] ARMv7: add PSCI supp
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.
Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/proc-armv/ptrace.h | 2 ++
arch
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/nonsec_virt.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
From: Ma Haijun
Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.
[maz: collapsed 3 patches into one, rewrote commit message]
Signed-off-by: Ma Haijun
Signed-off-by: Marc Zyngier
---
arch
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).
Signed-off-by: Marc Zyngier
---
arch/arm/cpu/armv7/Makefile | 4 ++
arch/arm/cpu/armv7/psci.S
1 - 100 of 190 matches
Mail list logo
