Hi YanHong,
On Wed, Mar 29, 2023 at 11:42:22AM +0800, Yanhong Wang wrote:
> Add initial u-boot device tree for the JH7110 RISC-V SoC.
>
> Signed-off-by: Yanhong Wang
> Tested-by: Conor Dooley
> ---
> arch/riscv/dts/jh7110-u-boot.dtsi | 99 +++
> 1 file changed, 99 i
Hi Tom,
The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79:
Merge tag 'u-boot-nand-20230417' of
https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 10:47:33
-0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/
On Mon, Sep 18, 2023 at 10:32:29AM +0200, Milan P. Stanić wrote:
> boot from SDIO3.0 (mmc sdcard) first if it is plugged.
> If mmc is not plugged try to boot from emmc if it is plugged.
> If emmc is not plugged then try to boot from nvme.
>
> Signed-off-by: Milan P. Stanić
> ---
> include/config
Hi Tom,
The following changes since commit c58ee1c9946a1550b1f6fee2b25da9ecc89baf71:
Merge branch '2023-09-19-tidy-up-some-kconfig-options' into next (2023-09-19
17:44:18 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
for you
Hi Tom,
The following changes since commit b9b83a86f0e84e837191db120c279a9cc0e3434b:
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
(2023-09-17 09:25:42 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
f
On Sat, Sep 23, 2023 at 01:53:30PM -0600, Simon Glass wrote:
> Hi Leo,
>
> On Wed, 20 Sept 2023 at 06:46, Leo Liang wrote:
> >
> > On Mon, Sep 18, 2023 at 10:32:29AM +0200, Milan P. Stanić wrote:
> > > boot from SDIO3.0 (mmc sdcard) first if it is plugged.
> >
On Fri, Sep 22, 2023 at 09:54:23PM +0800, Shengyu Qu wrote:
> Hello Leo,
>
> This patch seems only landed in next branch, not master. It is seriously
>
> needed to make visionfive 2 working properly. Could you merge it to
>
> master branch?
>
> Best regards,
>
> Shengyu
>
Hi Shengyu,
Got i
Hi Tom,
The following changes since commit 15155ab0a3d1f839509bcac620bfb38f950bead6:
Merge tag 'u-boot-imx-20230923' of
https://source.denx.de/u-boot/custodians/u-boot-imx (2023-09-24 17:15:31 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-ri
On Sat, Sep 23, 2023 at 01:35:26AM +0200, Heinrich Schuchardt wrote:
> Most boards don't enable the pre-console buffer. So we will not see any
> early messages. OpenSBI 1.3 provides us with the debug console extension
> that can fill this gap.
>
> For S-Mode U-Boot enable CONFIG_DEBUG_UART by defa
On Thu, Sep 21, 2023 at 10:42:18AM +0200, Heinrich Schuchardt wrote:
> Eliminating the C extension on application processors is under
> discussion.
>
> Support emitting a compressed instruction. This will lead to an
> illegal instruction exception if the C extension is not implemented.
>
> For te
On Thu, Sep 21, 2023 at 12:39:29PM +0200, Heinrich Schuchardt wrote:
> A 16 bit aligned instruction should generated an exception if the C
> extension is not available.
>
> Provide an 'extension ialign16' command for testing exception handling.
>
> For testing build qemu-riscv64_defconfig with CO
Hi Heinrich,
On Sat, Sep 23, 2023 at 01:35:26AM +0200, Heinrich Schuchardt wrote:
> Most boards don't enable the pre-console buffer. So we will not see any
> early messages. OpenSBI 1.3 provides us with the debug console extension
> that can fill this gap.
>
> For S-Mode U-Boot enable CONFIG_DEBU
On Mon, Sep 25, 2023 at 05:24:52PM +0800, Randolph wrote:
> Unify the memory layout for u-boot SPL mode
> Add "CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS"
>
> Signed-off-by: Randolph
> ---
> configs/ae350_rv32_spl_defconfig | 7 ---
> configs/ae350_rv32_spl_xip_defconfig | 5 +++--
> configs/ae3
Hi Heinrich,
On Tue, Sep 26, 2023 at 10:38:48AM +0200, Heinrich Schuchardt wrote:
> On 9/26/23 09:53, Leo Liang wrote:
> > Hi Heinrich,
> >
> > On Sat, Sep 23, 2023 at 01:35:26AM +0200, Heinrich Schuchardt wrote:
> > > Most boards don't enable the pre-con
Hi
On Thu, Sep 07, 2023 at 03:39:57PM +0900, Chanho Park wrote:
> Hi,
>
> > -Original Message-
> > From: Heinrich Schuchardt
> > Sent: Thursday, September 7, 2023 2:27 AM
> > To: Chanho Park ; Simon Glass
> >
> > Cc: u-boot@lists.denx.de; Rick Chen ; Leo
> >
> > Subject: Re: [PATCH v3
On Wed, Sep 06, 2023 at 02:18:13PM +0900, Chanho Park wrote:
> timer_get_boot_us function is required to record the boot stages as
> us-based timestamp.
> To get a micro-second time from a timer tick, this converts the
> formula like below to avoid zero result of (tick / rate) part.
>
> From: time
On Sun, Oct 01, 2023 at 07:40:47AM +0200, Heinrich Schuchardt wrote:
> Powering off the SiFive HiFive Unmatched board is supported both via the
> SBI and GPIO sysreset drivers. See device-tree entry
>
> compatible = "gpio-poweroff".
>
> Enable the poweroff command.
>
> Signed-off-by: Heinric
Hi Tom,
The following changes since commit 65b9b3462bec2966911658836983819ab4e4823e:
Merge branch 'next_pinctrl_sync' of
https://source.denx.de/u-boot/custodians/u-boot-sh (2023-10-02 15:19:02 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-ri
On Thu, Apr 27, 2023 at 11:56:58AM +0200, Heinrich Schuchardt wrote:
> Support for the VisionFive 2 board is not contained in the most recent
> OpenSBI release (v1.2).
>
> Signed-off-by: Heinrich Schuchardt
> ---
> doc/board/starfive/visionfive2.rst | 2 ++
> 1 file changed, 2 insertions(+)
Rev
On Fri, Apr 28, 2023 at 09:28:20AM +0800, Yanhong Wang wrote:
> Fixed errors reported when executing 'scripts/get_maintainer.pl -f
> configs/starfive_visionfive2_defconfig'.
>
> Invalid MAINTAINERS address: 'startfive'
>
> Signed-off-by: Yanhong Wang
> ---
> board/starfive/visionfive2/MAINTAINE
On Wed, Apr 12, 2023 at 10:38:16AM +0200, Heinrich Schuchardt wrote:
> OpenSBI already implements some extensions that are not ratified yet:
>
> * Debug Console Extension (DBCN)
> * System Suspend Extension (SUSP)
> * Collaborative Processor Performance Control Extension (CPPC)
>
> Allow the sbi
Hi Tom,
CI result:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
The following changes since commit 8ddaf943589756442bba21e5be645cd47526d82b:
Merge tag 'dm-pull-29apr21' of
https://source.denx.de/u-boot/custodians/u-boot-dm (2021-04-29 21:03:38 -0400)
are available
On Fri, May 07, 2021 at 09:09:43AM +0800, Tom Rini wrote:
> On Fri, May 07, 2021 at 09:06:33AM +0800, Leo Liang wrote:
>
> > Hi Tom,
> >
> > CI result:
> > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7400
> >
&g
h Rick.
I will update the information as soon as possible, thanks for the reminder.
And yes, please do CC your work to me, thanks again!
Best regards,
Leo
> On 5/6/21 9:06 PM, Leo Liang wrote:
> > Hi Tom,
> >
> > CI result:
> > https://source.denx.de/u-boot/custo
Hi Sean,
This patch series produces conflicts when applying.
Could you please rebase them? Thanks!
Best regards,
Leo
On Sun, Apr 11, 2021 at 11:57:57PM -0400, Sean Anderson wrote:
> Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc
> state for SPL only") it has been impossib
On Tue, Jul 25, 2023 at 05:46:47PM +0800, Minda Chen wrote:
> As the Designware_i2c_pci.c uses ACPI APIs, If some SoCs (StarFive
> JH7110) contain Designware i2c and PCI but do not use ACPI,
> This file will be can't be compiled. So add a new Kconfig for
> designware_i2c_pci.c, which depends on ACP
Hi Heinrich,
On Tue, Jul 25, 2023 at 09:44:00AM +0200, Heinrich Schuchardt wrote:
> On 7/25/23 04:26, Bin Meng wrote:
> > +Simon,
> >
> > On Tue, Jul 25, 2023 at 9:30 AM Heinrich Schuchardt
> > wrote:
> > >
> > > The pci_mmc.c driver can generate ACPI info and therefore includes
> > > asm/acpi_
On Wed, Jul 26, 2023 at 08:05:13AM +0200, Heinrich Schuchardt wrote:
> The pci_mmc.c driver can generate ACPI info and therefore includes
> asm/acpi_table.h. This file does not exist for the RISC-V architecture
> and thus code compilation fails when using this driver on RISC-V
>
> Create an empty
Hi Rick,
On Thu, Jul 27, 2023 at 09:27:31AM +0800, Rick Chen wrote:
> > Hi Rick,
> >
> > On Wed, 19 Apr 2023 at 00:56, Rick Chen wrote:
> > >
> > > Hi Simon,
> > >
> > > > Hi Rick,
> > > >
> > > > On Mon, 10 Apr 2023 at 01:26, Rick Chen wrote:
> > > > >
> > > > > Allow U-Boot to load 32 or 64 bi
On Fri, Jul 28, 2023 at 03:54:15PM +0200, Heinrich Schuchardt wrote:
> The EFI_RNG_PROTOCOL is needed for Linux' KASLR.
>
> QEMU can provide a virtio-rng device to emulate a hardware random number
> generator which is supported by our virtio_rng driver.
>
> Enabling CONFIG_DM_RNG will enable CONF
invoking QEMU.
>
> Reported-by: Leo Liang
> Signed-off-by: Heinrich Schuchardt
> ---
> See related patch
> [PATCH 1/1] riscv: qemu: imply CONFIG_DM_RNG
> https://lists.denx.de/pipermail/u-boot/2023-July/525293.html
>
> The non-spl defconfigs still don't scan virtio
Hi Tom,
The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9:
Merge tag 'x86-pull-20230801' of
https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-risc
Hi Bin,
On Wed, Aug 02, 2023 at 02:27:29PM +0800, Bin Meng wrote:
> Hi Leo,
>
> On Wed, Aug 2, 2023 at 1:49 PM Leo Liang wrote:
> >
> > Hi Tom,
> >
> > The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9:
> >
> >
Hi Tom,
The following changes since commit 7755b2200777f72dca87dd169138e95f011bbcb9:
Merge tag 'x86-pull-20230801' of
https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-ris
On Wed, Aug 02, 2023 at 10:39:46PM +0200, Heinrich Schuchardt wrote:
> The SBI specification v2.0-rc2 defines new extensions:
>
> * Nested Acceleration Extension (NACL)
> * Steal Time Accounting (STA)
>
> Allow the sbi command to display these.
>
> Add missing implementation IDs.
>
> Signed-off
On Tue, Aug 08, 2023 at 08:39:55PM +0800, Shengyu Qu wrote:
> Add a Kconfig item to allow SPL to clear stack/GD/malloc area before
> using them.
>
> Signed-off-by: Bo Gan
> Signed-off-by: Shengyu Qu
> ---
> arch/riscv/Kconfig | 8
> 1 file changed, 8 insertions(+)
Reviewed-by: Leo Yu-
Hi Shengyu,
On Tue, Aug 08, 2023 at 08:39:56PM +0800, Shengyu Qu wrote:
> Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
> existing Starfive JH7110's L2 LIM clean code, since existing code has
> following issues:
> 1. Each hart (in the middle of a function call) overwriting it
On Tue, Aug 08, 2023 at 08:39:57PM +0800, Shengyu Qu wrote:
> Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE.
>
> Signed-off-by: Bo Gan
> Signed-off-by: Shengyu Qu
> ---
> arch/riscv/cpu/jh7110/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Lian
On Tue, Aug 08, 2023 at 09:14:36PM +0800, Shengyu Qu wrote:
> On Starfive Visionfive 2, the u-boot environment settings are saved to
> on-board SPI flash. Enable relative configs by default and set offset
> and size according to upstream linux dts.
>
> Signed-off-by: Shengyu Qu
> ---
> configs/s
On Mon, Aug 07, 2023 at 04:53:35PM +0800, Minda Chen wrote:
> Get the correct ECAM offset and record the secondary bus
> number in Multiple RC case.
>
> Signed-off-by: Minda Chen
> ---
> drivers/pci/pcie_plda_common.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Leo
On Mon, Aug 07, 2023 at 04:53:36PM +0800, Minda Chen wrote:
> In StarFive VF2 board. pcie0 connect to VTI usb controller.
> Enable it to support usb host.
>
> Signed-off-by: Minda Chen
> ---
> arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-
On Mon, Aug 07, 2023 at 04:53:37PM +0800, Minda Chen wrote:
> Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
> SYS_CACHE_SHIFT_6 to enable it.
>
> Signed-off-by: Minda Chen
> ---
> arch/riscv/cpu/jh7110/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Lian
On Mon, Aug 07, 2023 at 04:53:38PM +0800, Minda Chen wrote:
> Add XHCI_PCI to enable usb3-host functions.
> Also add usb command and keyboard config.
>
> Signed-off-by: Minda Chen
> ---
> configs/starfive_visionfive2_defconfig | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Leo Yu-Chi
On Wed, Aug 09, 2023 at 09:11:32PM +0800, Shengyu Qu wrote:
> Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
> existing Starfive JH7110's L2 LIM clean code, since existing code has
> following issues:
> 1. Each hart (in the middle of a function call) overwriting its own
> s
Hi Tom,
The following changes since commit ec58228830a1f68e8e65099387cf12c5a91c9e72:
Merge tag 'x86-pull-20230809' of
https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-09 13:17:34 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-risc
On Mon, Nov 20, 2023 at 02:35:31AM +, John Clark wrote:
> device tree overlay support requires fdtoverlay_addr_r to be set
>
> before
> ~~
> Invalid fdtoverlay_addr_r for loading overlays
>
> after
> ~
> Retrieving file: /boot/overlay/rtc-ds3231.dtbo
>
> Signed-off-by: John Clark
>
On Thu, Nov 16, 2023 at 09:01:34PM +0800, Randolph wrote:
> Add documentation to introduce the Falcon Mode on RISC-V.
> In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel.
>
> Signed-off-by: Randolph
> ---
> doc/develop/falcon.rst | 171 +
>
On Thu, Nov 16, 2023 at 09:01:35PM +0800, Randolph wrote:
> In Falcon Boot mode, the fdt blob should be move to the RAM from
> kernel BSS section. To avoid being cleared by BSS initialisation.
> SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
>
> Signed-off-by: Randolph
> ---
> board/Ande
On Thu, Nov 16, 2023 at 09:01:36PM +0800, Randolph wrote:
> Add the address where the FDT blob should be moved.
>
> Signed-off-by: Randolph
> ---
> configs/ae350_rv32_falcon_defconfig | 1 +
> configs/ae350_rv32_falcon_xip_defconfig | 1 +
> configs/ae350_rv64_falcon_defconfig | 1 +
> c
Hi Kuan Lim,
On Tue, Nov 28, 2023 at 02:42:33PM +0800, Kuan Lim Lee wrote:
> Add timer driver in Starfive SoC. It is an timer that outside
> of CPU core and inside Starfive SoC.
>
> Signed-off-by: Kuan Lim Lee
> Signed-off-by: Wei Liang Lim
>
> Changes for v2:
> - correct driver name, comment,
Hi Tom,
The following changes since commit 2f0282922b2c458eea7f85c500a948a587437b63:
Prepare v2024.01-rc4 (2023-12-04 13:46:56 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to 94533cd9c15a60b74420e53a72
On Thu, Nov 30, 2023 at 08:07:28PM +0800, Randolph wrote:
> This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
>
> Signed-off-by: CL Wang
> Signed-off-by: Randolph
> ---
> drivers/watchdog/Kconfig | 6 +
> drivers/watchdog/Makefile| 1 +
> drivers/watc
On Thu, Nov 30, 2023 at 08:07:29PM +0800, Randolph wrote:
> It adds the ATCWDT200 support for Andes AE350 platform.
> It also enables wdt command support.
>
> Signed-off-by: CL Wang
> Signed-off-by: Randolph
> ---
> configs/ae350_rv32_defconfig | 4
> configs/ae350_rv32_spl_defconf
On Tue, Oct 31, 2023 at 05:24:38PM +0900, Jaehoon Chung wrote:
> Add gpio-restart node to do reset.
>
> Before applied this patch, System Reset Extension doesn't appear with
> sbi command.
>
> OpenSBI 1.3
> Machine:
> Vendor ID 489
> Architecture ID 8007
> Implementation ID 4210
On Tue, Oct 31, 2023 at 05:24:39PM +0900, Jaehoon Chung wrote:
> Enable CONFIG_SYSREST config to do reset.
>
> Signed-off-by: Jaehoon Chung
> ---
> configs/starfive_visionfive2_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang
On Mon, Dec 11, 2023 at 10:22:10AM +0800, Jun Liang Tan wrote:
> From: Kuan Lim Lee
>
> Add timer driver in Starfive SoC. It is an timer that outside
> of CPU core and inside Starfive SoC.
>
> Signed-off-by: Kuan Lim Lee
> Signed-off-by: Wei Liang Lim
>
> Changes for v2:
> - correct driver na
Hi Tom,
On Thu, Dec 14, 2023 at 07:19:02AM -0500, Tom Rini wrote:
> On Thu, Dec 14, 2023 at 10:38:07AM +0800, Leo Yu-Chi Liang(梁育齊) wrote:
>
> > Hi Tom,
> >
> > The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151:
> >
> > Merge tag 'u-boot-imx-20231212' of
> > https:/
Hi Tom,
The following changes since commit fdefb4e194c65777fa11479119adaa71651f41d4:
Merge tag 'efi-next-20231217' of
https://source.denx.de/u-boot/custodians/u-boot-efi into next (2023-12-17
09:11:06 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/
On Thu, Dec 14, 2023 at 02:09:36PM +, Zong Li wrote:
> This driver is currently responsible for enabling the clock gating
> feature of SiFive pre core's private L2 cache.
>
> Signed-off-by: Zong Li
> ---
> drivers/cache/Kconfig| 7 +
> drivers/cache/Makefile | 1 +
On Thu, Dec 14, 2023 at 02:09:37PM +, Zong Li wrote:
> The power gating feature of pl2 should be enabled as early as possible,
> it would be better to put it in SPL stage.
>
> Signed-off-by: Zong Li
> ---
> arch/riscv/lib/sifive_cache.c | 21 +
> 1 file changed, 21 insert
On Wed, Dec 20, 2023 at 03:53:28PM +0100, Michal Simek wrote:
> Extend compatible string to match the latest change in dt binding.
>
> Fixes: 7576ab2facae ("riscv: Add support for AMD/Xilinx MicroBlaze V")
> Signed-off-by: Michal Simek
> ---
>
> dt binding patch is available here.
> https://lore
Hi Tom,
The following changes since commit 4b151562bb8e54160adedbc6a1c0c749c00a2f84:
bootmeth: pass size to efi_binary_run() (2023-12-22 10:36:50 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git next
for you to fetch changes up to 992
On Wed, May 15, 2024 at 04:04:30PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> Node offsets returned by libfdt can contain negative error numbers, so
> the variable type should be "int". As things stand, if the ethernet
> nodes are not found in the early init callback, the if (node < 0) t
On Wed, May 15, 2024 at 04:04:31PM +0100, Conor Dooley wrote:
> From: Conor Dooley
>
> A given AMP configuration for a board may make either one, or neither
> of, the ethernet ports available to U-Boot. The Icicle's init code will
> fail if mac1 is not present, so move it to the optional approach
Hi Tom,
The following changes since commit 46ff00bea5dd2dd247d5e2fdadbf5dcf8653cd9a:
Merge tag 'tpm-master-27052024' of
https://source.denx.de/u-boot/custodians/u-boot-tpm (2024-05-27 08:56:02 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-ri
On Fri, Jun 07, 2024 at 10:41:17AM +0200, Heinrich Schuchardt wrote:
> The firmware invoking main U-Boot uses
>
> * a0 to pass the boot hart
> * a1 to pass a device-tree
>
> Let the bdinfo command print this information, e.g.
>
> boot hart = 0x001b
> firmware fdt= 0x000
On Wed, Jun 19, 2024 at 05:22:52PM +0200, Heinrich Schuchardt wrote:
> Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with
> assembly file") reduced the alignment of function smh_trap().
>
> As described in the "RISC-V Semihosting" specification [1] the ssli,
> ebreak, and srai
On Mon, Jun 24, 2024 at 11:46:58AM +0200, Andreas Schwab wrote:
> Fixes: 44a792c994 ("riscv: sifive: unmatched: migrate to text environment")
> Signed-off-by: Andreas Schwab
> ---
> board/sifive/unmatched/unmatched.env | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-C
On Thu, Jul 11, 2024 at 12:55:05PM -0700, E Shattow wrote:
> [EXTERNAL MAIL]
>
> Ping. This regression still exists and is now in stable release.
> Should we revert this change or how must it be fixed?
>
> -E
>
Hi all,
I think I could revert this commit for now
if we cannot find the root caus
Hi Tom,
The following changes since commit 5024a96db8ea6ff2e814f4599af9e5faf09296b7:
Subtree merge tag 'v6.10-dts' of devicetree-rebasing repo [1] into
dts/upstream (2024-07-20 11:15:22 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
On Fri, Dec 29, 2023 at 04:32:21PM +0800, Randolph wrote:
> Add documentation to introduce the Falcon Mode on RISC-V.
> In this mode, the boot sequence is SPL -> OpenSBI -> Linux kernel.
>
> Signed-off-by: Randolph
> ---
> doc/develop/falcon.rst | 158 +
>
On Fri, Dec 29, 2023 at 04:32:22PM +0800, Randolph wrote:
> In Falcon Boot mode, the fdt blob should be move to the RAM from
> kernel BSS section. To avoid being cleared by BSS initialisation.
> SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
>
> Signed-off-by: Randolph
> ---
> board/Ande
On Fri, Dec 29, 2023 at 04:32:23PM +0800, Randolph wrote:
> Add the address to which the FDT blob is to be moved.
>
> Signed-off-by: Randolph
> ---
> configs/ae350_rv32_falcon_defconfig | 1 +
> configs/ae350_rv32_falcon_xip_defconfig | 1 +
> configs/ae350_rv64_falcon_defconfig | 1 +
>
On Wed, Jan 10, 2024 at 09:17:44PM +0100, Aurelien Jarno wrote:
> The difference between the StarFive VisionFive 2 1.2A and 1.3B boards is
> handled dynamically by looking at the PCB version in the EEPROM in order
> to have a single u-boot version for both versions of the board. While
> the "model"
On Wed, Jan 10, 2024 at 09:26:53PM +0100, Aurelien Jarno wrote:
> QEMU RISC-V supports multiple virtio devices, but only tries to boot to
> the first one. Enable support for a second virtio device, that is useful
> for instance to boot on a disk image + an installer. Ideally that should
> be made d
On Tue, Jan 16, 2024 at 02:35:57PM +0800, Nylon Chen wrote:
> From: Vincent Chen
>
> LEDs and multiple fans can be controlled by SPL. This patch ensures
> that all fans have been enabled in the SPL stage. In addition, the
> LED's color will be set to yellow.
>
> Signed-off-by: Vincent Chen
> Co
On Wed, Jan 17, 2024 at 05:46:52PM +0100, Heinrich Schuchardt wrote:
> Detect and show if the SBI implements the Debug Trigger Extension.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/include/asm/sbi.h | 1 +
> cmd/riscv/sbi.c | 1 +
> 2 files changed, 2 insertions(+)
R
On Sat, Jan 27, 2024 at 02:48:45PM +0100, Aurelien Jarno wrote:
> The VisionFive 2 board supports saving the u-boot environment settings
> are saved to on-board SPI flash. However the defconfig enables both
> ENV_IS_NOWHERE and ENV_IS_IN_SPI_FLASH, preventing the "saveenv" command
> to work. Fix th
On Sun, Jan 28, 2024 at 03:05:24PM +0800, Kongyang Liu wrote:
> Import device tree from Linux kernel to add basic support for CPU, PLIC,
> UART and Timer. The name cv1800b in the filename represent the chip used
> on Milk-V Duo board.
>
> Signed-off-by: Kongyang Liu
> ---
>
> Changes in v4:
> -
On Sun, Jan 28, 2024 at 03:05:25PM +0800, Kongyang Liu wrote:
> Add support for Sophgo's Milk-V Duo board, only minimal device tree and
> serial console are enabled, and it can boot via vendor first stage
> bootloader.
>
> Signed-off-by: Kongyang Liu
> ---
>
> (no changes since v3)
>
> Changes
On Sun, Jan 28, 2024 at 03:05:26PM +0800, Kongyang Liu wrote:
> Add document for Milk-V Duo board which based on Sophgo's CV1800B SoC.
>
> Signed-off-by: Kongyang Liu
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Add brief description of the procedure to run u-boot-dtb.bin
>
> doc/bo
On Sun, Jan 28, 2024 at 08:22:47PM +0100, Lukasz Tekieli wrote:
> This ports the pad drive strength register configuration which can be
> already found in the Linux driver for this PHY.
>
> Signed-off-by: Lukasz Tekieli
> ---
> drivers/net/phy/motorcomm.c | 130 ++
On Sun, Jan 28, 2024 at 08:22:48PM +0100, Lukasz Tekieli wrote:
> Configure the pad drive strength register for both PHYs.
> The values correspond to what can be found in the Linux DTS
> for VisionFive2 v1.3b.
>
> Pad drive strength configuration is required for the phy0 to work correctly
> with 1
On Mon, Jan 29, 2024 at 09:43:08AM +0100, Nam Cao wrote:
> JH7110 has a power management unit controller node. Add this node.
>
> This device is used by OpenSBI during board reset/shutdown.
>
> Signed-off-by: Nam Cao
> ---
> arch/riscv/dts/jh7110.dtsi | 6 ++
> 1 file changed, 6 insertions(
On Mon, Jan 29, 2024 at 09:43:09AM +0100, Nam Cao wrote:
> Add the axp15060 regulator device. OpenSBI uses this device to perform
> board reset and shutdown.
>
> Signed-off-by: Nam Cao
> ---
> v2: "stf,axp15060-regulator" -> "x-powers,axp15060" to match Linux.
>
> arch/riscv/dts/jh7110-starfive
Hi Tom,
The following changes since commit 28760ce8640ff6266bd1c1c568a4a231576f3919:
Merge tag 'clk-2024.04-rc2' of
https://source.denx.de/u-boot/custodians/u-boot-clk (2024-01-30 07:54:28 -0500)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.
On Mon, Nov 06, 2023 at 08:13:15AM +0900, Chanho Park wrote:
> Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110
> watchdog device.
>
> Signed-off-by: Chanho Park
> ---
> drivers/clk/starfive/clk-jh7110.c | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by: Leo Yu-
On Mon, Nov 06, 2023 at 08:13:16AM +0900, Chanho Park wrote:
> Add to support StarFive watchdog driver. The driver is imported from
> linux kernel's drivers/watchdog/starfive-wdt.c without jh7100 support
> because there is no support of jh7100 SoC in u-boot yet.
> Howver, this patch has been kept t
On Mon, Nov 06, 2023 at 08:13:17AM +0900, Chanho Park wrote:
> Adds jh7110 watchdog device tree node.
>
> Signed-off-by: Chanho Park
> ---
> arch/riscv/dts/jh7110.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Mon, Nov 06, 2023 at 08:13:18AM +0900, Chanho Park wrote:
> Enables StarFive Watchdog driver and WDT command.
>
> Signed-off-by: Chanho Park
> ---
> configs/starfive_visionfive2_defconfig | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Mon, Nov 06, 2023 at 12:56:47PM +0100, Michal Simek wrote:
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor.
>
> The patch contains initial wiring and configuration for initial HW design
> with memory, cpu, inter
On Wed, Apr 17, 2024 at 04:01:27PM +0200, Heinrich Schuchardt wrote:
> OpenSBI has implemented the Supervisor Software Events Extension.
> Allow detecting it in the sbi command.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/include/asm/sbi.h | 1 +
> cmd/riscv/sbi.c | 1
On Wed, Apr 17, 2024 at 04:01:28PM +0200, Heinrich Schuchardt wrote:
> Let the sbi command detect the coreboot and oreboot SBI Implementation IDs
> defined in SBI specification v2.0.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> cmd/riscv/sbi.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewe
On Sat, Apr 20, 2024 at 03:08:25PM +0800, Kongyang Liu wrote:
> Add configs related to spi nor flash for Sophgo Milk-V Duo board
>
> Signed-off-by: Kongyang Liu
> ---
>
> configs/milkv_duo_defconfig | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Sat, Apr 20, 2024 at 03:08:24PM +0800, Kongyang Liu wrote:
> Add spi nor flash controller node for cv18xx SoCs
>
> Signed-off-by: Kongyang Liu
> ---
>
> arch/riscv/dts/cv1800b-milkv-duo.dts | 13 +
> arch/riscv/dts/cv18xx.dtsi | 17 +
> 2 files changed,
On Sat, Apr 20, 2024 at 03:08:23PM +0800, Kongyang Liu wrote:
> Add spi nor flash controller driver for cv1800b SoC
>
> Signed-off-by: Kongyang Liu
> ---
>
> drivers/spi/Kconfig| 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/cv1800b_spif.c | 321
On Sat, Apr 20, 2024 at 03:00:28PM +0800, Kongyang Liu wrote:
> Add ethernet node for cv1800b SoC
>
> Signed-off-by: Kongyang Liu
> ---
>
> Changes in v2:
> - Change compatible
> - Add clocks and interrupt properties.
>
> arch/riscv/dts/cv1800b-milkv-duo.dts | 7 ++-
> arch/riscv/dts/cv18
On Thu, Apr 11, 2024 at 05:29:45PM +0800, Yu Chien Peter Lin wrote:
> The instruction and data cache line sizes of Andes core
> are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so
> the SYS_CACHELINE_SIZE is enabled with a default value.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/risc
On Tue, Apr 16, 2024 at 03:52:40PM +0800, Kongyang Liu wrote:
> Add sysreset configs as well as poweroff and reset commands for Sophgo
> Milk-V Duo board.
>
> Signed-off-by: Kongyang Liu
> ---
>
> configs/milkv_duo_defconfig | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Leo Yu-Chi Li
On Tue, Apr 16, 2024 at 03:52:39PM +0800, Kongyang Liu wrote:
> Bind cv1800b sysreset driver for Sophgo Milk-V Duo board in board_init
> function.
>
> Signed-off-by: Kongyang Liu
> ---
>
> board/sophgo/milkv_duo/board.c | 4
> 1 file changed, 4 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
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