On Wed, Jun 19, 2024 at 05:22:52PM +0200, Heinrich Schuchardt wrote:
> Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with
> assembly file") reduced the alignment of function smh_trap().
>
> As described in the "RISC-V Semihosting" specification [1] the ssli,
> ebreak, and srai statements must all reside in the same memory page.
>
> [1] RISC-V Semihosting, Version 0.4, 12th June 2024
> https://github.com/riscv-non-isa/riscv-semihosting
>
> Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with
> assembly file")
> Signed-off-by: Heinrich Schuchardt <heinrich.schucha...@canonical.com>
> ---
> arch/riscv/lib/semihosting.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com>
