Hi Tom, The following changes since commit 4b151562bb8e54160adedbc6a1c0c749c00a2f84:
bootmeth: pass size to efi_binary_run() (2023-12-22 10:36:50 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to 9924d44dbcd47bd3664fa9f1f9f24044d83eaebf: andes: ae350: Enable MISC_INIT_R for ae350 platform (2023-12-27 17:29:11 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19106 ---------------------------------------------------------------- - Andes: Enable Andes CPU memboost and ECC feature by default - Sifive: Add private L2 cache driver ---------------------------------------------------------------- Leo Yu-Chi Liang (6): andes: csr.h: Clean up CSR definition andes: ae350: Implement cache switch via Kconfig andes: cpu: Enable memboost feature andes: cpu: Enable cache and TLB ECC support andes: ae350: Save cpu name to env andes: ae350: Enable MISC_INIT_R for ae350 platform Michal Simek (1): riscv: Extend board compatible string with "qemu,mbv" Zong Li (2): cache: add sifive private L2 cache driver riscv: cache: support cache enable in SPL stage arch/riscv/cpu/andesv5/cpu.c | 33 ++++++++++++++++++------- arch/riscv/dts/xilinx-mbv32.dts | 2 +- arch/riscv/include/asm/arch-andes/csr.h | 29 +++++++++++++--------- arch/riscv/include/asm/csr.h | 1 + arch/riscv/lib/sifive_cache.c | 21 ++++++++++++++++ board/AndesTech/ae350/ae350.c | 26 ++++++++++++++++++- configs/ae350_rv32_defconfig | 5 ++-- configs/ae350_rv32_spl_defconfig | 5 ++-- configs/ae350_rv32_spl_xip_defconfig | 5 ++-- configs/ae350_rv32_xip_defconfig | 5 ++-- configs/ae350_rv64_defconfig | 5 ++-- configs/ae350_rv64_spl_defconfig | 5 ++-- configs/ae350_rv64_spl_xip_defconfig | 5 ++-- configs/ae350_rv64_xip_defconfig | 5 ++-- drivers/cache/Kconfig | 7 ++++++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-pl2.c | 44 +++++++++++++++++++++++++++++++++ 17 files changed, 165 insertions(+), 39 deletions(-) create mode 100644 drivers/cache/cache-sifive-pl2.c Best regards, Leo
