Hi Tom, The following changes since commit ec58228830a1f68e8e65099387cf12c5a91c9e72:
Merge tag 'x86-pull-20230809' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-09 13:17:34 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 47ed15125cccd98e041cdff3b6bbe675a2418ec2: riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE (2023-08-10 10:58:55 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17276 ---------------------------------------------------------------- + Add USB host support on VisionFive2 board + Enable SPI flash support on VisionFive2 board + Enable Random Number Generator in RISC-V QEMU board + Display new SBI extension + Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM (Loosely-Integrated Memory) ---------------------------------------------------------------- Heinrich Schuchardt (2): riscv: qemu: imply CONFIG_DM_RNG cmd/sbi: display new extensions Minda Chen (4): pci: plda: Get correct ECAM offset in multiple PCIe RC case riscv: dts: starfive: Enable pcie0 dts node riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support Shengyu Qu (4): configs: starfive: Enable environment in SPI flash support riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch/riscv/Kconfig | 8 ++++++++ arch/riscv/cpu/jh7110/Kconfig | 2 ++ arch/riscv/cpu/jh7110/spl.c | 25 ------------------------- arch/riscv/cpu/start.S | 12 ++++++++++++ arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +- arch/riscv/include/asm/sbi.h | 2 ++ board/emulation/qemu-riscv/Kconfig | 1 + cmd/riscv/sbi.c | 4 ++++ common/init/board_init.c | 3 +++ configs/starfive_visionfive2_defconfig | 14 ++++++++++++++ drivers/pci/pcie_plda_common.c | 5 +++-- 11 files changed, 50 insertions(+), 28 deletions(-) Best regards, Leo
