Hi, Jagan,
I tested my driver based on your sf quad changes, and it is ok. For the
sf quad functions, I didn' t test, because my driver doesn't support sf quad
now.
Thanks.
Best Regards,
Alison Wang
> -Original Message-
> From: Jagan Teki [mailto:jagannadha.sutradharud
Hi, Jagan,
Could you help to review the series? Thanks.
Best Regards,
Alison Wang
On Monday 13 January 2014 02:24 PM, Huan Wang wrote:
> Hi, Jagan,
>
> I tested my driver based on your sf quad changes, and it is ok. For the
> sf quad functions, I didn'
Hi, Jan,
>
> CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
> be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
> boards that support CONFIG_ARMV7_NONSEC, and it only works on those.
>
> CC: Tang Yuantian
> CC: York Sun
> CC: Steve Rae
> CC: Andre Pr
York,
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, April 30, 2015 1:36 AM
> To: u-boot@lists.denx.de
> Cc: Wang Huan-B18965; Sun York-R58495
> Subject: [PATCH] arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h
>
> ccsr_ddr structure is already def
Verified on board ls1021qds.
Regards,
Alison.
> -Original Message-
> From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net]
> Sent: Thursday, September 18, 2014 7:25 PM
> To: Tang Yuantian-B29983
> Cc: Wang Huan-B18965; Lu Jingchang-B35083; Jin Zhengxiong-R64188;
> Kushwaha Prabhakar-B32
Hi, Albert,
> On Thu, 18 Sep 2014 13:47:13 +0800, Alison Wang
> wrote:
>
> > For the pblimage tool, the SPL image is splitted into 64 byte chunks,
> > and PBL needs a command for each piece. In current pblimage structure,
> > the size of the SPL image should be a fixed value. Well, for LS102xA
>
Hi, Albert,
> > + . = ALIGN(4);
> > + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
> > +
> > + . = ALIGN(4);
> > + .data : {
> > + *(.data*)
> > + }
> > +
> > + . = ALIGN(4);
> > + .u_boot_list : {
> > + KEEP(*(SORT(.u_boot_list*_i2c_*)));
> > + }
Hi, Albert,
> > > On Thu, 18 Sep 2014 13:47:13 +0800, Alison Wang
> > >
> > > wrote:
> > >
> > > > For the pblimage tool, the SPL image is splitted into 64 byte
> > > > chunks, and PBL needs a command for each piece. In current
> > > > pblimage structure, the size of the SPL image should be a fix
Hi, Albert,
> On Thu, 18 Sep 2014 13:47:14 +0800, Alison Wang
> wrote:
>
> > @@ -111,6 +115,14 @@ static void pbl_parser(char *name)
> > size_t len = 0;
> >
> > fname = name;
> > +
> > + if (strstr(fname, "ls102xa")) {
> > + next_pbl_cmd = 0x8101a000;
> > + pbl_cmd_
Hi, Albert,
> > On Thu, 18 Sep 2014 13:47:18 +0800, Alison Wang
> > wrote:
> >
> > > +
> > > + . = ALIGN(4);
> > > + .u_boot_list : {
> > > + KEEP(*(SORT(.u_boot_list*_i2c_*)));
> > > + }
> >
> > IS this required? And if it is, could it not be added to the
> > arch/arm/cpu
Hi, York,
> On 09/21/2014 11:17 PM, Wang Huan-B18965 wrote:
> >
> > [Alison Wang] Let me explain the sequence.
> >
> > 1. u-boot-spl.bin is produced. The size of it is not a fixed value.
> >
> > 2. u-boot-spl-pbl-pad.bin is produced. The size of it is defined by
> > CONFIG_SPL_MAX_SIZE. For detail
Hi, Albert,
> On Mon, 22 Sep 2014 06:22:44 +0000, Huan Wang
> wrote:
>
> > Hi, Albert,
> >
> > > On Thu, 18 Sep 2014 13:47:14 +0800, Alison Wang
> > >
> > > wrote:
> > >
> > > > @@ -111,6 +115,14
Hi, York,
> On 9/22/14 7:43 PM, "Wang Huan-B18965"
> wrote:
>
> >Hi, York,
> >
> >> On 09/21/2014 11:17 PM, Wang Huan-B18965 wrote:
> >> >
> >> > [Alison Wang] Let me explain the sequence.
> >> >
> >> > 1. u-boot-spl.bin is produced. The size of it is not a fixed value.
> >> >
> >> > 2. u-boot-s
Hi, Albert,
> On Mon, 22 Sep 2014 06:46:20 +0000, Huan Wang
> wrote:
>
> > Hi, Albert,
> >
> > > > On Thu, 18 Sep 2014 13:47:18 +0800, Alison Wang
> > > >
> > > > wrote:
> > > >
> > > > > +
> > >
Hi, Prabhakar,
> On 9/29/2014 8:23 AM, Alison Wang wrote:
> > SCFG_SCFGREVCR is SCFG bit reverse register. This register must be
> > written with 0x before writing to any other SCFG register.
> > Then other SCFG register could be written in big-endian mode.
> >
> > Address: 157_h base
Hi, Albert,
> On Mon, 29 Sep 2014 10:53:11 +0800, Alison Wang
> wrote:
>
> > From: Jason Jin
> >
> > Disable the snoop for slave interface 0, 1 and 2 to avoid the
> > interleaving on the CCI400 BUS.
>
> Please be more specific: this patch specifically targets arch ls102xa
> and some associate
Hi, Albert,
> On Thu, 25 Sep 2014 06:45:00 +0000, Huan Wang
> wrote:
>
> > Hi, Albert,
> >
> > > On Mon, 22 Sep 2014 06:46:20 +, Huan Wang
> > > wrote:
> > >
> > > > Hi, Albert,
> > > >
> > > >
Hi, Albert,
> On Wed, 8 Oct 2014 09:53:03 +0000, Huan Wang
> wrote:
>
> > Hi, Albert,
> >
> > > On Thu, 25 Sep 2014 06:45:00 +, Huan Wang
> > > wrote:
> > >
> > > > Hi, Albert,
> > > >
> > > > > O
Hi, York,
> On 09/26/2014 03:33 AM, Alison Wang wrote:
> > This patch adds SD boot support for LS1021ATWR board. SPL framework
> is
> > used. PBL initialize the internal RAM and copy SPL to it, then SPL
> > initialize DDR using SPD and copy u-boot from SD card to DDR, finally
> > SPL transfer cont
Hi, York,
> On 09/26/2014 03:33 AM, Alison Wang wrote:
> > This patch adds SD boot support for LS1021AQDS board. SPL framework
> is
> > used. PBL initialize the internal RAM and copy SPL to it, then SPL
> > initialize DDR using SPD and copy u-boot from SD card to DDR, finally
> > SPL transfer cont
Hi, York,
> On 09/26/2014 03:33 AM, Alison Wang wrote:
> > For LS102xA, interactive DDR debugger is still needed in SPL part.
> > So build the needed files in SPL image too.
> >
> > Signed-off-by: Alison Wang
> > ---
> > Change log:
> > v2: No change.
> >
> > common/Makefile | 20 ++
Hello, Albert,
> On Fri, 17 Oct 2014 16:00:30 +0800, Alison Wang
> wrote:
> > To support interactive DDR debugger, cli_simple.o, cli.o,
> > cli_readline.o, command.o, s_record.o, xyzModem.o and cmd_disk.o are
> > all needed for drivers/ddr/fsl/interactive.c.
> >
> > In current common/Makefile, th
Hi, Fabio,
On Fri, May 30, 2014 at 4:23 AM, Alison Wang wrote:
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "ethaddr=00:e0:0c:bc:e5:60\0" \
> + "eth1addr=00:e0:0c:bc:e5:61\0" \
> + "eth2addr=00:e0:0c:bc:e5:62\0" \
> + "eth3addr=00:e0:0c:bc:e5:63\0" \
> + "ip
Hi, Yuantian,
> From: Tang Yuantian
>
> Freescale ARM-based Layerscape LS102xA contain a SATA controller which
> comply with the serial ATA 3.0 specification and the AHCI 1.3
> specification.
> This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
>
> Signed-off-by: Tang Yuantian
>
Hi, zhuoyu,
> -Original Message-
> From: Zhuoyu Zhang [mailto:zhuoyu.zh...@freescale.com]
> Sent: Friday, August 07, 2015 7:49 PM
> To: Sun York-R58495
> Cc: u-boot@lists.denx.de; Jin Zhengxiong-R64188; Wang Huan-B18965
> Subject: [PATCH] arm/ls102xa:add hwconfig setting to support disable
Acked-by: Alison Wang
Tested-by: Alison Wang
Best Regards,
Alison Wang
> -Original Message-
> From: Claudiu Manoil [mailto:claudiu.man...@freescale.com]
> Sent: Wednesday, August 12, 2015 6:29 PM
> To: Sun York-R58495
> Cc: Wang Huan-B18965; u-boot@lists.denx.de
> Subject: [PATCH] ls10
> -Original Message-
> From: Alexander Stein [mailto:alexander.st...@systec-electronic.com]
> Sent: Wednesday, August 12, 2015 9:56 PM
> To: u-boot@lists.denx.de; Albert Aribaud; Jingchang Lu; Kushwaha
> Prabhakar-B32579; Wang Huan-B18965; Jin Zhengxiong-R64188; Wang Huan-
> B18965; Sun Yo
> On 11/23/2015 11:19 PM, Alexander Stein wrote:
> > On Monday 23 November 2015 10:51:49, York Sun wrote:
> >> On 11/04/2015 12:19 AM, Alexander Stein wrote:
> >>> When reading a large blob. e.g. a linux kernel (several MiBs) a
> >>> watchdog timeout might occur meanwhile. So pet the watchdog while
Hi, York,
> On Wednesday 25 November 2015 02:20:53, Huan Wang wrote:
> > [Alison Wang] I didn't meet any issue when using sf commands to write
> > and read the serial flash.
> >
> > Hi, Alexander,
> >
> > Could you show me the detail commands and pr
> On Thursday 03 December 2015 09:49:40, Huan Wang wrote:
> > [Alison Wang] I could not reproduce the issue. Maybe I don't have the
> > external watchdog which will reset after ~1.5s as Alexander mentioned.
>
> Could you try to set the internal watchdog to 1s timeout
> On 12/03/2015 01:49 AM, Wang Huan-B18965 wrote:
>
>
>
> >>
> >> The actual command which results in a watchdog reset is 'sf read
> >> 0x8104 0x20 0x40'. Please note that this uses an external
> >> watchdog which is enabled by default and resets after ~1.5s. The
> >> command itself
York,
Ok, I will rebase.
Best Regards,
Alison Wang
> -Original Message-
> From: Sun York-R58495
> Sent: Saturday, August 01, 2015 1:16 AM
> To: Wang Huan-B18965; u-boot@lists.denx.de
> Cc: Wang Huan-B18965
> Subject: Re: [PATCH] armv8: fsl-lsch3: Rewrite MMU translation table
> e
Acked-by: Alison Wang
Tested-by: Alison Wang
Best Regards,
Alison Wang
> -Original Message-
> From: Zhang Zhuoyu-B46552
> Sent: Friday, July 31, 2015 2:02 PM
> To: Sun York-R58495
> Cc: u-boot@lists.denx.de; Jin Zhengxiong-R64188; Wang Huan-B18965; Wang
> Dongsheng-B40534
> Subject: R
York,
> On 08/02/2015 07:48 PM, Alison Wang wrote:
> > This patch rewrites MMU translation table entries to achieve:
> > a) Start with all table entries as "invalid".
> > b) Rewrite the table entries as "device-ngnrne" for cache-inhibit
> > access.
> > c) Rewrite the table entries as "normal" for
Hi, Alexander,
> On Tuesday 04 August 2015 09:55:37, Alison Wang wrote:
> > This patch addresses a problem mentioned recently on this mailing
> list:
> > [1].
> >
> > In that posting a LS1021 based system was locking up at about 5
> > minutes after boot,but the problem was mysteriously related to
Hi,
I tested this set on my LS1021ATWR board. NOR boot using DUART as
serial output is ok. But NOR boot using LPUART as serial output failed. How
about your test result?
Best Regards,
Alison Wang
> -Original Message-
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Thursda
Hi, Bin,
> On Wed, Jan 6, 2016 at 1:31 PM, Huan Wang wrote:
> > Hi,
> >
> > I tested this set on my LS1021ATWR board. NOR boot using DUART
> as serial output is ok. But NOR boot using LPUART as serial output
> failed. How about your test result?
> >
Hi, dongsheng,
It looks ok for me.
Acked-by: Alison Wang
Best Regards,
Alison Wang
> -Original Message-
> From: Wang Dongsheng-B40534
> Sent: Wednesday, July 15, 2015 10:11 AM
> To: Wang Huan-B18965; Kushwaha Prabhakar-B32579
> Cc: Wang Huan-B18965; u-boot@lists.denx.de; jan.kis...@sie
Hi, Mark
> -Original Message-
> From: Mark Rutland [mailto:mark.rutl...@arm.com]
> Sent: Wednesday, July 15, 2015 5:14 PM
> To: Wang Huan-B18965
> Cc: Sun York-R58495; u-boot@lists.denx.de; Wang Huan-B18965;
> marc.zyng...@arm.com
> Subject: Re: [U-Boot] [PATCH] arm: ls1021a: Ensure LS1021
Hi, Mark,
> > On Wed, Jul 15, 2015 at 08:13:05AM +0100, Alison Wang wrote:
> > > This patch addresses a problem mentioned recently on this mailing
> > list:
> > > [1].
> > >
> > > In that posting a LS1021 based system was locking up at about 5
> > > minutes after boot, but the problem was mysterio
Hi, Marc,
>>> On Wed, Jul 15, 2015 at 08:13:05AM +0100, Alison Wang wrote:
This patch addresses a problem mentioned recently on this mailing
>>> list:
[1].
In that posting a LS1021 based system was locking up at about 5
minutes after boot, but the problem was mysteriously
Hi, Mark,
On Fri, Jul 17, 2015 at 11:01:01AM +0100, Huan Wang wrote:
> Hi, Mark,
>
> > > On Wed, Jul 15, 2015 at 08:13:05AM +0100, Alison Wang wrote:
> > > > This patch addresses a problem mentioned recently on this mailing
> > > list:
> > > > [1]
Hello Albert,
> On Wed, 9 Sep 2015 10:22:02 +0800, Alison Wang
> wrote:
> > When building u-boot with the latest Linaro toolchain, such as
> > gcc-linaro-4.9, u-boot will hang at PCIE init on LS1021A platform.
> > The issue is reported on
> > http://comments.gmane.org/gmane.linux.linaro.toolchai
Hi, Mark and Alexander,
Do you have any comment about this patch?
Thanks.
Best Regards,
Alison Wang
> > On Tuesday 04 August 2015 09:55:37, Alison Wang wrote:
> > > This patch addresses a problem mentioned recently on this mailing
> > list:
> > > [1].
> > >
> > > In that posting
Reviewed-by: Alison Wang
Best Regards,
Alison Wang
> -Original Message-
> From: Yuan Yao [mailto:yao.y...@freescale.com]
> Sent: Wednesday, October 21, 2015 6:15 PM
> To: Sun York-R58495; Wang Huan-B18965
> Cc: u-boot@lists.denx.de
> Subject: [PATCH 1/5] arm: ls1021a: merge SoC specific
Hi, Alex,
> On 06/08/2016 07:14 AM, Alison Wang wrote:
> > To support loading a 32-bit OS, the execution state will change from
> > AArch64 to AArch32 when jumping to kernel.
> >
> > The architecture information will be got through checking FIT
> > image, then U-Boot will load 32-bit OS or 64-bit
> > Am 15.06.2016 um 05:04 schrieb Huan Wang :
> >
> > Hi, Alex,
> >
> >>> On 06/08/2016 07:14 AM, Alison Wang wrote:
> >>> To support loading a 32-bit OS, the execution state will change from
> >>> AArch64 to AArch32 when jumping to
> On 15.06.16 10:08, Huan Wang wrote:
> >>> Am 15.06.2016 um 05:04 schrieb Huan Wang :
> >>>
> >>> Hi, Alex,
> >>>
> >>>>> On 06/08/2016 07:14 AM, Alison Wang wrote:
> >>>>> To support loading a 32-bit OS,
Hi, Alex,
> > Am 15.06.2016 um 05:04 schrieb Huan Wang :
> >
> > Hi, Alex,
> >
> >>> On 06/08/2016 07:14 AM, Alison Wang wrote:
> >>> To support loading a 32-bit OS, the execution state will change from
> >>> AArch64 to AArch32 when jump
> On 30.06.16 09:16, Huan Wang wrote:
> > Hi, Alex,
> >
> >>> Am 15.06.2016 um 05:04 schrieb Huan Wang :
> >>>
> >>> Hi, Alex,
> >>>
> >>>>> On 06/08/2016 07:14 AM, Alison Wang wrote:
> >>>>> To s
Hi, Alex,
As there is strong objection to remove the codes about switching
to EL1, I think we have to remain it, do you agree?
If it is remained, I think your suggestion about *always*
jumping to ep for both switching to AArch64 and AArch32 modes will make the
cod
Hi, York,
> On 03/28/2016 02:16 PM, Ed Swarthout wrote:
> > When switching between the early and final mmu tables, the stack will
> > get corrupted if the Non-Secure attribute is different. For ls1043a,
> > this issue is currently masked because flush_dcache_all is called
> > before the switch wh
> On 04/18/2016 08:36 PM, Huan Wang wrote:
> > Hi, York,
> >
> >> On 03/28/2016 02:16 PM, Ed Swarthout wrote:
> >>> When switching between the early and final mmu tables, the stack
> >>> will get corrupted if the Non-Secure attribute is different. F
Hi, York,
> -Original Message-
> From: york sun [mailto:york@nxp.com]
> Sent: Tuesday, February 02, 2016 1:06 AM
> To: Aneesh Bansal; u-boot@lists.denx.de; Huan Wang-B18965
> Cc: Ruchika Gupta; Prabhakar Kushwaha; Nitesh Lal
> Subject: Re: [PATCH v3] Enable snoopi
> On 16.02.2016 07:54, Thomas Chou wrote:
> > After commit a058052c358c
> > ("net: phy: do not read configuration register on reset")
> >
> > both 3c120 and 10m50 devboard which use Marvel m88es PHY got this
> > error message,
> >
> > Net: eth0: ethernet@400
> > => ping 192.168.1.5
> > ethern
Hi, York,
> On 02/08/2016 04:57 PM, York Sun wrote:
> > Since a recent merge 5160def "dm: lpuart: Drop the legacy code",
> > ls1021aqds_ddr4_nor_lpuart and ls1021aqds_nor_lpuart failed to compile
> > because they are using legacy driver for lpuart. Following ls1021atwr,
> > ls1021aqds should be co
on.org.uk;
> hdego...@redhat.com; albert.u.b...@aribaud.net; s...@denx.de;
> alison.w...@freescale.com; york sun; Huan Wang
> Subject: [RFC PATCH v1 1/2] arm: ls1021aqds: Convert to driver model and
> enable serial support
>
> Split duart configuration as device tree file. Move /chosen nod
Hi, York,
> On Tue, Feb 9, 2016 at 8:57 AM, York Sun wrote:
> > Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart to driver
> > model suport. Enable lpuart port driver.
> >
> > Signed-off-by: York Sun
> > CC: Alison Wang
> > CC: Bin Meng
> >
> > ---
> >
> > arch/arm/dts/Makefile
> On Sun, Feb 21, 2016 at 9:00 PM, Fabio Estevam
> wrote:
> > On Sun, Feb 21, 2016 at 8:31 AM, Stefano Babic wrote:
> >> Hi Bhuvanchandra,
> >>
> >> your applied patch:
> >>
> >> commit 5160def267739518950e8e3bb78e0e6c3941cb3e
> >> Author: Bhuvanchandra DV
> >> Date: Wed Jan 27 10:31:52 2016 +
Hi, Bin,
> On Wed, Feb 24, 2016 at 11:56 AM, Alison Wang
> wrote:
> > In general, a carriage return needs to execute before a line feed.
> > The patch is to change serial DM driver based on this rule.
> >
> > Signed-off-by: Alison Wang
> > ---
> > drivers/serial/serial-uclass.c | 5 +++--
> > 1
On Tue, Feb 23, 2016 at 3:01 AM, York Sun wrote:
> Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart to driver
> model suport. Enable lpuart port driver.
>
> Signed-off-by: York Sun
> CC: Alison Wang
> CC: Bin Meng
>
> ---
>
> Changes in v2:
> Fix default device tree name for
> ls1
On Tue, Feb 23, 2016 at 3:01 AM, York Sun wrote:
> Split duart configuration as device tree file. Move /chosen node out
> of board commone device tree. Convert ls1021aqds nor and SD
> configurations to driver model support (qspi already uses DM).
> Enable ns16550 DM serial driver for nor configura
Hi, Bin,
> On Wed, Feb 24, 2016 at 3:35 PM, Huan Wang wrote:
> > Hi, Bin,
> >
> >> On Wed, Feb 24, 2016 at 11:56 AM, Alison Wang
> >> wrote:
> >> > In general, a carriage return needs to execute before a line feed.
> >> > T
Hi, Bin,
> On Thu, Feb 25, 2016 at 10:41 AM, Alison Wang
> wrote:
> > In general, a carriage return needs to execute before a line feed.
> > The patch is to change some serial drivers based on this rule, such as
> > serial_mxc.c, serial_pxa.c, serial_s3c24x0.c and usbtty.c.
> >
> > Signed-off-by:
Hi, Bin,
> On Thu, Feb 25, 2016 at 11:02 AM, Huan Wang wrote:
> > Hi, Bin,
> >
> >> On Thu, Feb 25, 2016 at 10:41 AM, Alison Wang
> >> wrote:
> >> > In general, a carriage return needs to execute before a line feed.
> >> > The patch
Hi, Bin,
> On Thu, Feb 25, 2016 at 11:02 AM, Huan Wang wrote:
> > Hi, Bin,
> >
> >> On Thu, Feb 25, 2016 at 10:41 AM, Alison Wang
> >> wrote:
> >> > In general, a carriage return needs to execute before a line feed.
> >> > The patch
Hi, Jim,
> -Original Message-
> From: James Chargin [mailto:jimccr...@gmail.com]
> Sent: Thursday, February 25, 2016 10:19 PM
> To: u-boot@lists.denx.de; b18...@freescale.com
> Subject: Re: [U-Boot] [PATCH] serial: Move carriage return before line
> feed for some serial drivers
>
> This i
> On 13.05.16 10:40, Alison Wang wrote:
> > To support loading a 32-bit OS, the execution state will change from
> > AArch64 to AArch32 when jumping to kernel.
> >
> > The architecture information will be got through checking FIT image,
> > then U-Boot will load 32-bit OS or 64-bit OS automatically
> On 05/13/2016 01:50 AM, Alison Wang wrote:
> > To support loading a 32-bit OS, the execution state will change from
> > AArch64 to AArch32 when jumping to kernel.
> >
> > The architecture information will be got through checking FIT image,
> > then U-Boot will load 32-bit OS or 64-bit OS automati
> On 16.05.16 07:28, Huan Wang wrote:
> >> On 13.05.16 10:40, Alison Wang wrote:
> >>> To support loading a 32-bit OS, the execution state will change from
> >>> AArch64 to AArch32 when jumping to kernel.
> >>>
> >>> The architecture info
> On 05/19/2016 10:26 AM, Alison Wang wrote:
> > To support loading a 32-bit OS, the execution state will change from
> > AArch64 to AArch32 when jumping to kernel.
> >
> > The architecture information will be got through checking FIT image,
> > then U-Boot will load 32-bit OS or 64-bit OS automati
> On 20.05.16 08:53, Huan Wang wrote:
> >> On 05/19/2016 10:26 AM, Alison Wang wrote:
> >>> To support loading a 32-bit OS, the execution state will change from
> >>> AArch64 to AArch32 when jumping to kernel.
> >>>
> >>> The arc
> On 20.05.16 10:26, Huan Wang wrote:
> >> On 20.05.16 08:53, Huan Wang wrote:
> >>>> On 05/19/2016 10:26 AM, Alison Wang wrote:
> >>>>> To support loading a 32-bit OS, the execution state will change
> >>>>> from
> >>>>
Hi, York,
> On 05/26/2016 01:51 AM, Alison Wang wrote:
> > To support loading a 32-bit OS, the execution state will change from
> > AArch64 to AArch32 when jumping to kernel.
> >
> > The architecture information will be got through checking FIT image,
> > then U-Boot will load 32-bit OS or 64-bit
> On 26.05.16 10:41, Alison Wang wrote:
> > To support loading a 32-bit OS, the execution state will change from
> > AArch64 to AArch32 when jumping to kernel.
> >
> > The architecture information will be got through checking FIT image,
> > then U-Boot will load 32-bit OS or 64-bit OS automatically
> On 03.06.16 05:11, Huan Wang wrote:
> >> On 26.05.16 10:41, Alison Wang wrote:
> >>> To support loading a 32-bit OS, the execution state will change from
> >>> AArch64 to AArch32 when jumping to kernel.
> >>>
> >>> The architecture info
Hi,
> -Original Message-
> From: Matthias Fuchs [mailto:matthias.fu...@esd.eu]
> Sent: Tuesday, January 13, 2015 5:34 AM
> To: u-boot@lists.denx.de
> Cc: Wang Huan-B18965; Matthias Fuchs
> Subject: [PATCH] m68k: remove TASREG board
>
> Signed-off-by: Matthias Fuchs
> ---
> arch/m68k/Kco
Hi, York,
> On 11/13/2014 06:12 AM, Alison Wang wrote:
> > CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
> > S0 will cause CAAM self test failure. This patch is to enable
> snooping
> > for S0 slave interface.
> >
> > Signed-off-by: Alison Wang
> > ---
> > board/freescale
York,
> On 01/15/2015 01:29 AM, Alison Wang wrote:
> > CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
> > S0 will cause CAAM self test failure. This patch is to enable
> snooping
> > for S0 slave interface. These CCI-400 operations are moved to
> > board_early_init_f() to be
York,
> On 01/08/2015 09:13 PM, Alison Wang wrote:
> > There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for
> > using the same SMMU3 on LS1021A.
> >
> > Signed-off-by: Xiubo Li
> > Signed-off-by: Alison Wang
> > ---
> > arch/arm/include/asm/arch-ls102xa/config.h | 1 +
Hi, Sinan Akman,
As the comment of commit c207ff612903389f8b32e377fe32be43e6efd8f7 said,
we removes the bit reversing for SCFG registers in u-boot. It is implemented
through PBI command in RCW.
.pbi
write 0x570200, 0x
.end
Through this way, other SCFG registers could be
Hi, Tom,
> On Thu, Jan 15, 2015 at 04:08:40PM +0100, Angelo Dureghello wrote:
> > Dear all,
> >
> > i would like to post a patch with the m68k generic board support,
> > tested and working here, but of course not tested for all the other
> > m68k boards except mine.
> >
> > My coldfire board is th
> On 18.07.16 05:24, Huan Wang wrote:
> > Hi, Alex,
> >
> >
> >
> > As there is strong objection to remove the codes about
> > switching to EL1, I think we have to remain it, do you agree?
>
> I agree, yes.
>
> >
Hi,
> On 08/29/2016 11:29 AM, Huan Wang wrote:
> >> On 18.07.16 05:24, Huan Wang wrote:
> >>> Hi, Alex,
> >>>
> >>>
> >>>
> >>>As there is strong objection to remove the codes
> >>> a
> On 08/29/2016 11:29 AM, Huan Wang wrote:
> >> On 18.07.16 05:24, Huan Wang wrote:
> >>> Hi, Alex,
> >>>
> >>>
> >>>
> >>>As there is strong objection to remove the codes
> >>> a
> > On 08/29/2016 11:29 AM, Huan Wang wrote:
> > >> On 18.07.16 05:24, Huan Wang wrote:
> > >>> Hi, Alex,
> > >>>
> > >>>
> > >>>
> > >>>As there is strong objection to remove the codes
&g
Hi, Jagan,
> On 03/03/2016 01:06 PM, york sun wrote:
> > On 02/29/2016 04:26 AM, Jagan Teki wrote:
> >> Hi York,
> >>
> >> On 27 February 2016 at 02:14, york sun wrote:
> >>> On 02/22/2016 10:18 AM, Jagan Teki wrote:
>
>
>
>
> Can you pls- test the dataflash changes? use u-boot-spi/s
Hi, Simon,
> On 1 March 2016 at 02:06, Alison Wang wrote:
> > When LCD/HDMI is connected to LS1021ATWR or LS1021AQDS, the console
> > output should be shown on the monitor.
> >
> > If CONFIG_DM_SERIAL and CONFIG_DM_STDIO are both enabled, serial
> > device is registered and added to the stdio lis
Hi, Jagan,
> On 9 March 2016 at 13:37, Qianyu Gong wrote:
> > Hi Jagan,
> >
> >> -Original Message-
> >> From: york sun
> >> Sent: Tuesday, March 08, 2016 12:46 AM
> >> To: Jagan Teki ; Huan Wang ;
> >> Qianyu Gong
> >&g
Hi, Vincent,
> On 03/24/2016 01:17 AM, Vincent wrote:
> > Hi,
> > I started to port my kernel to the secure world on a LS1021a board, so
> > I started to read the reference manual on the CSU component. In Table
> > 9.8, we can see that
> >
> > - Debug EPU is CSL47[24:16]
> > - DDDI is CSL48[24:16]
> Original Message
> Subject: [PATCH] arm: Fix order of CSU indexes in ns_access.h
> Date: 03/29/2016 12:41 AM
> From: Vincent Siles
> To: u-boot@lists.denx.de
> CC: vincent.si...@provenrun.com ,
> york...@freescale.com , Mingkai Hu
> , Gong Qianyu ,
> Albert Aribaud , Hou Zhiqi
Hi, York and Scott,
> On 04/05/2016 05:11 AM, Alison Wang wrote:
> > For LS1021A Secure Boot, SPARE2 register is used and modified by the
> > IBR. To avoid the conflict, SPARE4 is used instead of SPARE2 to store
> > the entry point of kernel. This patch is to get the entry point of
> > kernel from
Hi, Scott,
> On 04/05/2016 09:16 PM, Huan Wang wrote:
> > Hi, York and Scott,
> >
> >> On 04/05/2016 05:11 AM, Alison Wang wrote:
> >>> For LS1021A Secure Boot, SPARE2 register is used and modified by the
> >>> IBR. To avoid the conflict, SPARE4 is
Hi,
> -Original Message-
> From: Bin Meng [mailto:bmeng...@gmail.com]
> Sent: Thursday, January 14, 2016 11:39 AM
> To: Simon Glass; Stefan Agner; Bhuvanchandra DV; Albert ARIBAUD (3ADEV);
> York Sun; Alison Wang; U-Boot Mailing List
> Subject: [PATCH v2 9/9] arm: ls1021atwr: Enable driver
Hi, york,
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Wednesday, November 26, 2014 5:23 AM
> To: Wang Huan-B18965; u-boot@lists.denx.de
> Cc: Jin Zhengxiong-R64188; Wang Huan-B18965
> Subject: Re: [PATCH] arm: ls102xa: Add QSPI boot support for
> LS1021AQDS
Hi, York,
> On 11/17/2014 11:02 PM, Albert ARIBAUD wrote:
> > Hello York,
> >
> > On Mon, 17 Nov 2014 15:00:42 -0800, York Sun
> > wrote:
> >> On 10/27/2014 06:48 PM, Wang Huan-B18965 wrote:
> >>> Hello, Albert,
> >>>
> >>
> >>
> > ---
> > Change log:
> > v3: Gave more explaination
Hi, Yamada,
> On Wed, 3 Dec 2014 15:00:45 +0800
> Alison Wang wrote:
>
> > Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and
> > LS1021ATWR.
> >
> > Signed-off-by: Alison Wang
> > ---
> > Change log:
> > v4: New file.
> >
> > arch/arm/Kconfig | 2 ++
> > 1 file changed, 2 inserti
Hi, York,
> On 12/09/2014 01:38 AM, Alison Wang wrote:
> > This patch adds QSPI boot support for LS1021AQDS/TWR board.
> > The QSPI boot image need to be programmed into the QSPI flash first.
> > Then the booting will start from QSPI memory space.
> >
> > Signed-off-by: Alison Wang
> > ---
> > Ch
York,
> > On 12/09/2014 01:38 AM, Alison Wang wrote:
> > > This patch adds QSPI boot support for LS1021AQDS/TWR board.
> > > The QSPI boot image need to be programmed into the QSPI flash first.
> > > Then the booting will start from QSPI memory space.
> > >
> > > Signed-off-by: Alison Wang
> > >
Hi, York,
> On 10/29/2014 11:26 PM, Chao Fu wrote:
> > From: Chao Fu
> >
> > Configure ls1021a scfg register for QSPI clock initalization.
> >
> > Signed-off-by: Chao Fu
> > Signed-off-by: Alison Wang
> > ---
> > arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
> > board/freescale/ls10
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