Hey André,
On 31-12-2018 00:23, André Przywara wrote:
On 29/12/2018 22:10, Olliver Schinagl wrote:
Hi Olliver,
Luckily we have had no problem with this on our boards, but its sad to
see this patch reverted due to the buggy ddr implementation ...
This whole SPL is quite a sensitive construct
Hello,
This enables the bmp command (with gzip support enabled) on all
Raspberry Pi boards.
Changes in v2:
- added a commit fixing the int-to-pointer-cast warning on aarch64
Adam Heinrich (2):
cmd: bmp: Make integer-to-pointer cast platform independent
rpi: Enable command bmp
cmd/bmp.c
This patch fixes the int-to-pointer-cast warning on aarch64.
Signed-off-by: Adam Heinrich
---
cmd/bmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/bmp.c b/cmd/bmp.c
index b8af784590..00f0256a30 100644
--- a/cmd/bmp.c
+++ b/cmd/bmp.c
@@ -57,7 +57,7 @@ struct bmp_image
This patch enables the bmp command (with gzip support enabled) on all
Raspberry Pi boards.
The value of CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (required by
CONFIG_VIDEO_BMP_GZIP) is set to match resolution of the "official"
7 inch LCD.
Signed-off-by: Adam Heinrich
Cc: Alexander Graf
---
configs/rpi_0_
Hi Simon,
> Hi Lukasz,
>
> On Wed, 19 Dec 2018 at 03:11, Lukasz Majewski wrote:
> >
> > Dear Simon and Simon,
> >
> > > Am 05.12.2018 um 14:57 schrieb Simon Glass:
> > > > This option has crept into use with some boards. Add a warning
> > > > to try to prevent this.
> > > >
> > > > As an exa
Hi
On Mon, Dec 31, 2018 at 11:34:51AM +0100, Olliver Schinagl wrote:
> Hey André,
>
> On 31-12-2018 00:23, André Przywara wrote:
> > On 29/12/2018 22:10, Olliver Schinagl wrote:
> >
> > Hi Olliver,
> >
> > > Luckily we have had no problem with this on our boards, but its sad to
> > > see this p
On 31/12/2018 11:27, Michael Trimarchi wrote:
> Hi
>
> On Mon, Dec 31, 2018 at 11:34:51AM +0100, Olliver Schinagl wrote:
>> Hey André,
>>
>> On 31-12-2018 00:23, André Przywara wrote:
>>> On 29/12/2018 22:10, Olliver Schinagl wrote:
>>>
>>> Hi Olliver,
>>>
Luckily we have had no problem with
Hi
On Mon, Dec 31, 2018 at 01:10:43PM +, André Przywara wrote:
> On 31/12/2018 11:27, Michael Trimarchi wrote:
> > Hi
> >
> > On Mon, Dec 31, 2018 at 11:34:51AM +0100, Olliver Schinagl wrote:
> >> Hey André,
> >>
> >> On 31-12-2018 00:23, André Przywara wrote:
> >>> On 29/12/2018 22:10, Olliv
Hi Lukasz,
On Mon, 31 Dec 2018 at 04:26, Lukasz Majewski wrote:
>
> Hi Simon,
>
> > Hi Lukasz,
> >
> > On Wed, 19 Dec 2018 at 03:11, Lukasz Majewski wrote:
> > >
> > > Dear Simon and Simon,
> > >
> > > > Am 05.12.2018 um 14:57 schrieb Simon Glass:
> > > > > This option has crept into use with so
Although the previous version[1] is properly handled the clock gates
with enable and disable management, but this series is trying to add
some more complex Allwinner CLK architecture by handling parent clock
and other CLK attributes.
Allwinner Clock control unit comprises of parent clocks, gates,
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/ccu.h | 65 +++
Add common reset driver for all Allwinner SoC's.
Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table d
Add initial clock driver for Allwinner H3/H5.
- Implement USB bus and USB clocks via ccu_clk_gate table for
H3/H5, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table for
H3/H5, so it can accessed in common res
Add initial clock driver for Allwinner A83T.
- Implement USB bus and USB clocks via ccu_clk_gate table
for A83T, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for A83T, so it can accessed in common reset
Add initial clock driver for Allwinner A10/A20.
- Implement USB ahb and USB clocks via ccu_clk_gate table
for A10/A20, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10/A20,
so it can accessed in common reset dea
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a23.c | 6 ++
drivers/clk/sunxi/clk_a31.c | 7 +++
drivers/clk/sunxi/clk_a64.c | 6 ++
drivers/clk/sunxi/clk_a83t.c | 6 ++
drivers/clk/s
Add initial clock driver for Allwinner R40.
- Implement USB bus and USB clocks via ccu_clk_gate
for R40, so it can accessed in common clk enable
and disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for R40, so it can accessed in common reset deassert
Add initial clock driver for Allwinner A23/A33.
- Implement USB bus and USB clocks via ccu_clk_gate table
for A23/A33, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for A23/A33, so it can accessed in comm
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
Implement SPI AHB, MOD clocks and resets for Allwinner A64.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a64.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 1d0cd98183..09ff871aee 100644
--- a/drivers/clk/sunxi/c
Implement SPI AHB and MOD clocks for Allwinner A10/A20
and A10s/A13 SoC clock drivers via ccu clock gate table.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a10.c | 9 +
drivers/clk/sunxi/clk_a10s.c | 7 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/clk/sunxi/cl
Add Allwinner sun6i SPI driver for A31, H3/H5 an A64.
Cc: Fahad Sadah
Signed-off-by: Jagan Teki
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile| 1 +
drivers/spi/sun6i_spi.c | 398
3 files changed, 405 insertions(+)
create mode 100644 dr
Add initial clock driver for Allwinner A10s/A13.
- Implement USB ahb and USB clocks via ccu_clk_gate table
for A10s/A13, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB resets via ccu_reset table for A10s/A13,
so it can accessed in common reset
Add initial clock driver for Allwinner A31.
- Implement USB ahb1 and USB clocks via ccu_clk_gate table
for A31, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB ahb1 and USB resets via ccu_reset table
for A31, so it can accessed in common reset d
CLK and DM_RESET drivers are now available for most
of the Allwinner platforms, so enable in mach-sunxi/Kconfig
Enabling CLK will select DM_RESET by default.
Signed-off-by: Jagan Teki
---
arch/arm/mach-sunxi/Kconfig | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach
Now Allwinner platform is all set to use Generic USB
controller drivers, so remove the legacy sunxi drivers.
Cc: Marek Vasut
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/usb/host/Makefile | 2 -
drivers/usb/host/ehci-sunxi.c | 204 -
drivers/
Add reset_valid to check whether given reset is valid
or not.
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
include/reset.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/reset.h b/include/reset.h
index bc495a90c2..65aa7a4ce5 100644
--- a/include/reset.h
+++ b/include/
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a10.c | 9 +
drivers/clk/sunxi/clk_a10s.c | 5 +
drivers/clk/sunxi/clk_a23.c | 6 ++
drivers/clk/sunxi/clk_a31.c | 7 +++
drivers/clk/sun
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on musb driver.
Cc: Marek Vasut
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/usb/musb-new/sunxi.c | 81 ++--
1 file changed, 40 insertions(+), 41 deletions(
Clock control unit comprises of parent clocks, gates, multiplexers,
dividers, multipliers, pre/post dividers and flags etc.
So, the U-Boot implementation of ccu has divided into gates and tree.
gates are generic clock configuration of enable/disable bit management
which can be handle via ccu_clock
Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26
Author: Rodrigo Exterckötter Tjäder
Date: Wed Sep 26 19:48:24 2018 +
arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay
This should be a part of previous sync pa
Sopine has Winbond SPI flash, so enable the same to use
flash on Sopine board.
Cc: TL Lim
Signed-off-by: Jagan Teki
---
.../dts/sun50i-a64-sopine-baseboard-u-boot.dtsi | 16
configs/sopine_baseboard_defconfig | 7 +++
2 files changed, 23 insertions(+)
creat
Add initial clock driver for Allwinner V3S.
- Implement USB bus and USB clocks via ccu_clk_gate table
for V3S, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for V3S, so it can accessed in common reset dea
Once of key blocker for using USB Generic host controller
drivers in Allwinner are CLK and RESET drivers, now these
available for USB usage.
So switch sunxi USB use EHCI and OHCI Generic controllers.
Enabling USB is wisely a board choise, So Enable USB_OHCI_HCD
where it already have USB_EHCI_HCD
Add CLK support to enable AHB and MOD SPI clocks
on sun4i_spi driver.
Signed-off-by: Jagan Teki
---
drivers/spi/sun4i_spi.c | 46 +++--
1 file changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c
index b86b5
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on phy driver.
Cc: Marek Vasut
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.c | 77 ---
1 file changed, 57 insertions(+), 20 deletions(-
On 12/31/18 5:59 PM, Jagan Teki wrote:
> Now clock and reset drivers are available for respective
> SoC's so use clk and reset ops on phy driver.
>
> Cc: Marek Vasut
> Signed-off-by: Jagan Teki
> Acked-by: Maxime Ripard
Reviewed-by: Marek Vasut
btw I hope this is planned for _after_ 2019.01
On 12/31/18 5:59 PM, Jagan Teki wrote:
> Now clock and reset drivers are available for respective
> SoC's so use clk and reset ops on musb driver.
>
> Cc: Marek Vasut
> Signed-off-by: Jagan Teki
> Acked-by: Maxime Ripard
> ---
> drivers/usb/musb-new/sunxi.c | 81 ++
On Tue, Jan 1, 2019 at 12:01 AM Marek Vasut wrote:
>
> On 12/31/18 5:59 PM, Jagan Teki wrote:
> > Now clock and reset drivers are available for respective
> > SoC's so use clk and reset ops on phy driver.
> >
> > Cc: Marek Vasut
> > Signed-off-by: Jagan Teki
> > Acked-by: Maxime Ripard
>
> Revi
Hey André,
On 31-12-2018 14:10, André Przywara wrote:
On 31/12/2018 11:27, Michael Trimarchi wrote:
Hi
On Mon, Dec 31, 2018 at 11:34:51AM +0100, Olliver Schinagl wrote:
Hey André,
On 31-12-2018 00:23, André Przywara wrote:
On 29/12/2018 22:10, Olliver Schinagl wrote:
Hi Olliver,
Luckily
On Sun, 2018-12-30 at 16:44 +0100, Marek Vasut wrote:
> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > These series of patches enable peripheral bitstream being
> > programmed into FPGA
> > to get the DDR up running. This's also called early IO release,
On Sun, 2018-12-30 at 16:46 +0100, Marek Vasut wrote:
> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This patch adds description on properties about file name used for
> > both
> > peripheral bitstream and core bitstream.
> >
> > Signed-off-by: Tien
On Sun, 2018-12-30 at 16:45 +0100, Marek Vasut wrote:
> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> > loa
On Sun, 2018-12-30 at 16:47 +0100, Marek Vasut wrote:
> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Update the default configuration file to enable the necessary
> > functionality
> > to get the SoCFPGA loadfs driver support. This would enable the
>
On Sun, 2018-12-30 at 16:51 +0100, Marek Vasut wrote:
> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add support for loading FPGA bitstream to get DDR up running before
> > U-Boot is loaded into DDR. Boot device initialization, generic
> > firmware
>
On Sun, 2018-12-30 at 16:54 +0100, Marek Vasut wrote:
> On 12/30/18 9:13 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Marek Vasut
> >
> > Update the default configuration file to enable the necessary
> > functionality
> > the get the kit working. That includes SPL SD/MMC support, USB, and
>
Hello,
I just updated my u-boot and found that it won't work on my banana pi m2
berry anymore, failing with the following message:
U-Boot SPL 2019.01-rc2-00116-g9735326fff (Dec 31 2018 - 12:46:51 +0100)
DRAM: 0 MiB
### ERROR ### Please RESET the board ###
The error was introduced in commit
a8011
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